print out port, component connections in graphviz-friendly style

ports get ComponentBase* owners
(incomplete, and the graphs are too huge at the moment)

rigel-sim/include/packet/packet.h

@@ -93,13 +93,13 @@ class Packet {
     int          _gcoreid; ///< global core ID (should REMOVE, use TID)
     int          _gtid;    ///< global thread ID
 
-    uint32_t     _gatomic_operand; /// global atomic operand
+    uint32_t     _gatomic_operand; ///< global atomic operand
 
     uint64_t     _birthday; ///< cycle this was constructed
 
     uint64_t     _id;       ///< unique (modulo 2^64) identifier assigned at creation
 
-    bool         _completed; /// has been fully serviced
+    bool         _completed; ///< has been fully serviced
 
 };
 

rigel-sim/include/port/port.h

@@ -9,6 +9,8 @@
 #include <iostream>
 #include <cassert>
 
+class ComponentBase;
+
 /// this base class is meaningless
 /// FIXME either get rid of or define a general port
 /// concept with meaning
@@ -81,13 +83,17 @@ class InPortBase : public PortBase {
 
     friend class PortManager<T>;
 
+    ComponentBase* owner() { return _owner; }
+    void owner(ComponentBase* o) { _owner = o; }
+
     bool ready() { return _ready; }
 
   private:
-    bool _valid; /// data is valid
-    bool _ready; /// ready to accept a message
-    T    data;
-    std::string _name; ///< port name
+    T    data;             ///< templated data payload
+    std::string _name;     ///< port name
+    ComponentBase* _owner; ///< owning Component
+    bool _valid;           ///< data is valid
+    bool _ready;           ///< ready to accept a message
 
 };
 
@@ -147,6 +153,9 @@ class OutPortBase : public PortBase {
 
     std::string name() { return _name; }
 
+    ComponentBase* owner() { return _owner; }
+    void owner(ComponentBase* o) { _owner = o; }
+
     std::string connection_name() { 
       if (_connection) {
         return _connection->name(); 
@@ -158,6 +167,7 @@ class OutPortBase : public PortBase {
     friend class PortManager<T>;
 
   private:
+    ComponentBase*  _owner;
     std::string     _name; ///< port name
     InPortBase<T>* _connection;
 

rigel-sim/include/port/portmanager.h

@@ -1,6 +1,7 @@
 
 #include <map>
 #include <iostream>
+#include <fstream>
 #include "util/util.h" // for ExitSim
 
 // forward declarations
@@ -34,6 +35,35 @@ class PortManager {
 
     }
 
+    static void DumpGraphviz() {
+
+      std::fstream portgraph;
+
+      portgraph.open("ports.dot", std::fstream::out);
+
+      portgraph << "digraph PortGraph {" << std::endl;
+
+      {
+        typename std::map< std::string, OutPortBase<T>* >::iterator it;
+        for ( it = OutPorts.begin(); it != OutPorts.end(); ++it ) {
+          portgraph << (*it).second->owner()->name() << "_" << (*it).second->owner()->id() << " -> ";
+          portgraph << (*it).first << " -> " << (*it).second->connection_name() << std::endl;
+        }
+      }
+      {
+        typename std::map< std::string, InPortBase<T>* >::iterator it;
+        for ( it = InPorts.begin(); it != InPorts.end(); ++it ) {
+          portgraph << (*it).second->owner()->name() << "_" << (*it).second->owner()->id() << " -> ";
+          portgraph << (*it).first << std::endl;
+        }
+      }
+
+      portgraph << "}";
+
+      portgraph.close();
+
+    }
+
     static void registerInPort( InPortBase<T>* p ) {
 
       typename std::map< std::string, InPortBase<T>* >::iterator it;

rigel-sim/include/sim/component_base.h

@@ -66,6 +66,7 @@ class ComponentBase {
     ////////////////////////////////////////////////////////////////////////////
 
     void printHierarchy( int indent = 0 );
+    void printGraphviz();
     void dumpHierarchy();
     void addChild( ComponentBase* c );
 

rigel-sim/src/cluster/cluster_cache_functional.cpp

@@ -38,11 +38,13 @@ ClusterCacheFunctional::ClusterCacheFunctional(
   for (int i = 0; i < coreside_ins.size(); i++) {
     std::string n = PortName( name(), id(), "coreside_in", i );
     coreside_ins[i] = new InPortCallback<Packet*>(n, mcb);
+    coreside_ins[i]->owner(this);
   }
 
   for (int i = 0; i < coreside_outs.size(); i++) {
     std::string n = PortName( name(), id(), "coreside_out", i );
     coreside_outs[i] = new OutPortBase<Packet*>(n);
+    coreside_outs[i]->owner(this);
   }
 
 }

rigel-sim/src/cluster/cluster_cache_structural.cpp

@@ -33,11 +33,13 @@ ClusterCacheStructural::ClusterCacheStructural(
   for (unsigned i = 0; i < coreside_ins.size(); i++) {
     std::string pname = PortName( name(), id(), "coreside_in", i );
     coreside_ins[i] = new InPortBase<Packet*>(pname);
+    coreside_ins[i]->owner(this);
   }
 
   for (unsigned i = 0; i < coreside_outs.size(); i++) {
     std::string pname = PortName( name(), id(), "coreside_out", i );
     coreside_outs[i] = new OutPortBase<Packet*>(pname);
+    coreside_outs[i]->owner(this);
   }
 
 }

rigel-sim/src/cluster/cluster_functional.cpp

@@ -23,7 +23,9 @@ ClusterFunctional::ClusterFunctional(
   // we like this because the cluster is contained, but the ccache is a separate object
   // we could instead try to use a DUMMY port object that basically does this assignment via attach
   from_interconnect = new InPortBase<Packet*>(  PortName(name(), id(), "in") );
+  from_interconnect->owner(this);
   to_interconnect   = new OutPortBase<Packet*>( PortName(name(), id(), "out") );
+  to_interconnect->owner(this);
 
   // the ccache will actually be responsible for reading, writing to the cluster's ports
   ccache = new ClusterCacheFunctional(cp, from_interconnect, to_interconnect);

rigel-sim/src/cluster/cluster_structural.cpp

@@ -23,7 +23,9 @@ ClusterStructural::ClusterStructural(
   // we like this because the cluster is contained, but the ccache is a separate object
   // we could instead try to use a DUMMY port object that basically does this assignment via attach
   from_interconnect = new InPortBase<Packet*>(  PortName(name(), id(), "in") );
+  from_interconnect->owner(this);
   to_interconnect   = new OutPortBase<Packet*>( PortName(name(), id(), "out") );
+  to_interconnect->owner(this);
 
   // the ccache will actually be responsible for reading, writing to the cluster's ports
   ccache = new ClusterCacheStructural(cp, from_interconnect, to_interconnect);

rigel-sim/src/core/core_functional.cpp

@@ -53,7 +53,9 @@ CoreFunctional::CoreFunctional(
   std::string pname_out = PortName(name(), id(), "cache_out");
   std::string pname_in  = PortName(name(), id(), "cache_in");
   to_ccache   =  new OutPortBase<Packet*>(pname_out);
+  to_ccache->owner(this);
   from_ccache =  new InPortBase<Packet*>(pname_in);
+  from_ccache->owner(this);
 
   // per thread init
   thread_state.resize(numthreads);

rigel-sim/src/interconnect/crossbar.cpp

@@ -28,9 +28,11 @@ CrossBar::CrossBar(
   // TODO: do elsewhere, and connect
   for (unsigned i = 0; i < inports.size(); i++) {
     inports[i] = new InPortBase<Packet*>( PortName(name(), id(), "in", i) );
+    inports[i]->owner(this);
   } 
   for (unsigned i = 0; i < outports.size(); i++) {
     outports[i] = new OutPortBase<Packet*>( PortName(name(), id(), "out", i) );
+    outports[i]->owner(this);
   }
 }
 

rigel-sim/src/interconnect/tree_network.cpp

@@ -29,9 +29,11 @@ TreeNetwork::TreeNetwork(
   // construct ports
   for (unsigned i = 0; i < leaf_inports.size(); i++) {
     leaf_inports[i] = new InPortBase<Packet*>( PortName(name(), id(), "leaf_in", i) );
+    leaf_inports[i]->owner(this);
   } 
   for (unsigned i = 0; i < leaf_outports.size(); i++) {
     leaf_outports[i] = new OutPortBase<Packet*>( PortName(name(), id(), "leaf_out", i) );
+    leaf_outports[i]->owner(this);
   }
 }
 

rigel-sim/src/port/port.cpp

@@ -7,10 +7,16 @@
 std::string PortName(std::string parent, int id, std::string suffix, int index) {
 
     std::stringstream port_name;
+#if 0
     port_name << parent << "[" << std::setw(4) << id << "]." << suffix;
     if (index >= 0) {
       port_name << "[" << std::setw(4) << index << "]";
     }
+#endif
+    port_name << parent << "_" << id << "_" << suffix;
+    if (index >= 0) {
+      port_name << "_" << index ;
+    }
     return port_name.str();
 
 }

rigel-sim/src/sim/component_base.cpp

@@ -41,6 +41,17 @@ ComponentBase::printHierarchy( int indent ) {
   }
 }
 
+/// print object hierarchy in graphviz dot format
+void 
+ComponentBase::printGraphviz() {
+  for(size_t i=0; i<children_.size(); ++i) {
+    // print this node
+    fprintf(stderr,"%s_%d -> ", name_.c_str(), id_);
+    fprintf(stderr,"%s_%d\n", children_[i]->name().c_str(), children_[i]->id());
+    children_[i]->printGraphviz();
+  }
+}
+
 /// add a child object to this parent
 void 
 ComponentBase::addChild( ComponentBase* c ) {

rigel-sim/src/tile/tile_new.cpp

@@ -25,7 +25,9 @@ TileNew::TileNew(
   // contruct ports with outside world
   // TODO: relocate construction?
   from_gnet = new InPortBase<Packet*>( PortName(name(), id(), "memside_in") );
+  from_gnet->owner(this);
   to_gnet   = new OutPortBase<Packet*>( PortName(name(), id(), "memside_out") );
+  to_gnet->owner(this);
   //< end contruction of ports
 
   // new interconnect