Added full switch source to noc_switch IP

pcores/noc_switch_v1_00_a/hdl/vhdl/switch/endOfPacket/endOfPacketDetector.vhd

@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity endOfPacketDetector is
+	port (
+		dataValid	: in std_logic;
+		flag		: in std_logic;
+		fifoEnable	: in std_logic;
+
+		endOfPacket	: out std_logic
+	);
+end entity endOfPacketDetector;
+
+architecture rtl of endOfPacketDetector is
+begin
+
+	endOfPacket <= dataValid and fifoEnable and flag;
+
+end architecture rtl;

pcores/noc_switch_v1_00_a/hdl/vhdl/switch/header/headerDecoder.vhd

@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.headerPkg.all;
+
+entity headerDecoder is
+		port (
+		data		: in std_logic_vector(dataWidth-1 downto 0);
+
+		destAddr	: out address;
+		prio		: out priority
+	);
+end entity headerDecoder;
+
+architecture rtl of headerDecoder is
+
+begin
+
+	destAddr <= extractAddress(data);
+	prio <= extractPrio(data);
+
+end architecture rtl;

pcores/noc_switch_v1_00_a/hdl/vhdl/switch/header/headerDetector.vhd

@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity headerDetector is
+	port (
+		clk 		: in std_logic;
+		reset 		: in std_logic;
+
+		readEnable	: in std_logic;
+		empty		: in std_logic;
+		endOfPacket	: in std_logic;
+
+		headerValid	: out std_logic
+	);
+end entity headerDetector;
+
+architecture rtl of headerDetector is
+
+	type state is (idle, packetTransfer);
+	signal state_p, state_n	: state;
+
+begin
+
+	nomem_output : process (state_p, readEnable, empty, endOfPacket) is
+	begin
+		-- default assignment
+		headerValid <= '0';
+
+		if state_p = idle then
+			headerValid <= not empty;
+		end if;
+
+	end process nomem_output;
+
+	nomem_nextState : process(state_p, empty, readEnable, endOfPacket) is
+	begin
+		-- default assignment
+		state_n <= state_p;
+
+		case state_p is
+			when idle => 
+				if empty='0' and readEnable='1' then
+					state_n <= packetTransfer;
+				end if;
+			when packetTransfer => 
+				if endOfPacket='1' and readEnable='1' then
+					state_n <= idle;
+				end if;
+		end case;
+
+	end process nomem_nextState;
+
+	mem_stateTransition : process (clk, reset) is
+	begin
+		if reset = '0' then
+			state_p <= idle;
+		elsif rising_edge(clk) then
+			state_p <= state_n;
+		end if;
+	end process mem_stateTransition;
+
+
+
+end architecture rtl;

pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/extTxPortSelect.vhd

@@ -0,0 +1,63 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.switchPkg.all;
+
+entity extTxPortSelect is
+	port (
+		rxPortNrIn 			: in portNr;
+		rxPortNrOut			: out portNr;
+
+		txPortIdle			: in std_logic_vector(numExtPorts-1 downto 0);
+		txPortWriteEnable	: out std_logic_vector(numExtPorts-1 downto 0);
+
+		txFifoReadEnable	: out std_logic;
+		txFifoEmpty			: in std_logic;
+
+		txPortNrOut			: out portNr;
+		rxPortWriteEnable	: out std_logic_vector(numPorts-1 downto 0)
+	);
+end entity extTxPortSelect;
+
+architecture rtl of extTxPortSelect is
+
+	function selectTxPort(txPortIdle: std_logic_vector(numExtPorts-1 downto 0)) return portNrWrapper is
+		variable result : portNrWrapper;
+	begin
+		result := (others => '0');
+		while result < numExtPorts loop
+			if txPortIdle(wrappedPortNrToInteger(result)) = '1' then
+				return result + numIntPorts;
+			end if;
+			result := result + 1;
+		end loop;
+		return result + numIntPorts;
+	end selectTxPort;
+
+begin
+
+	rxPortNrOut <= rxPortNrIn;
+
+	nomem_output:process(txPortIdle, txFifoEmpty, rxPortNrIn) is
+		variable txPortNr : portNrWrapper;
+	begin
+		-- default assignments
+		txPortWriteEnable <= (others => '0');
+		txFifoReadEnable <= '0';
+		rxPortWriteEnable <= (others => '0');
+		txPortNrOut <= (others => '-');
+
+		if txFifoEmpty = '0' then
+			txPortNr := selectTxPort(txPortIdle);
+			if txPortNr /= portNrUndefined then
+				txPortWriteEnable(wrappedPortNrToInteger(txPortNr-numIntPorts)) <= '1';
+				txFifoReadEnable <= '1';
+				txPortNrOut <= txPortNr;
+				rxPortWriteEnable(portNrToInteger(rxPortNrIn)) <= '1';
+			end if;
+		end if;
+
+	end process nomem_output;
+
+end architecture rtl;

pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/headerFetch.vhd

@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.headerPkg.all;
+
+entity headerFetch is
+	port (
+		clk 			: in std_logic;
+		reset 			: in std_logic;
+
+		headerIn		: in header;
+		endOfRxPacket	: in std_logic;
+		selected		: in std_logic;
+
+		headerOut		: out header
+	);
+end entity headerFetch;
+
+architecture rtl of headerFetch is
+
+	type state is (idle, packetTransfer);
+	signal state_p, state_n : state;	
+
+begin
+
+	nomem_output : process (state_p, headerIn) is
+	begin
+		-- default assignment
+		headerOut <= headerIn;
+
+		if state_p=packetTransfer then
+			headerOut.valid <= '0';
+		end if;
+
+	end process nomem_output;
+
+	nomem_nextState : process (state_p, selected, endOfRxPacket) is
+	begin
+		-- default assignment
+		state_n <= state_p;
+
+		case state_p is
+			when idle =>
+				if selected='1' then
+					state_n <= packetTransfer;
+				end if;
+			when packetTransfer => 
+				if endOfRxPacket='1' then
+					state_n <= idle;
+				end if;
+		end case;
+	end process nomem_nextState;
+
+
+	mem_stateTransition : process (clk, reset) is
+	begin
+		if reset = '0' then
+			state_p <= idle;
+		elsif rising_edge(clk) then
+			state_p <= state_n;
+		end if;
+	end process mem_stateTransition;
+
+
+end architecture rtl;

pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/headerSelect.vhd

@@ -0,0 +1,74 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.headerPkg.all;
+use work.utilPkg.all;
+use work.switchPkg.all;
+
+entity headerSelect is
+	port (
+		headerIn		: in headerArray(numPorts-1 downto 0);
+		selected		: out std_logic_vector(numPorts-1 downto 0);
+
+		dataValid		: out std_logic;
+		selectedRxPort	: out portNr;
+		selectedAddr	: out address
+	);
+end entity headerSelect;
+
+
+architecture rtl of headerSelect is
+
+	function selectHeaderWithPrio(headers:headerArray(numPorts-1 downto 0); searchedPrio:priority) return portNrWrapper is
+		variable rxPortNr : portNrWrapper;
+	begin
+		rxPortNr := (others => '0');
+		while rxPortNr<numPorts loop
+			if headers(wrappedPortNrToInteger(rxPortNr)).valid='1' then
+				if headers(wrappedPortNrToInteger(rxPortNr)).prio = searchedPrio then
+					return rxPortNr;
+				end if;
+			end if;
+			rxPortNr := rxPortNr + 1;
+		end loop;
+		return portNrUndefined;
+	end selectHeaderWithPrio;
+
+	function selectHeader(headers:headerArray(numPorts-1 downto 0)) return portNrWrapper is
+		variable rxPortNr : portNrWrapper;
+		variable pri : priority;
+	begin
+		pri := to_unsigned(numPriorities-1, priorityWidth);
+		loop
+			rxPortNr := selectHeaderWithPrio(headers,pri);
+			if rxPortNr /= portNrUndefined then
+				return rxPortNr;
+			end if;
+			exit when pri = to_unsigned(0, priorityWidth);
+			pri := pri-1; 
+		end loop;
+		return portNrUndefined;
+	end selectHeader;	
+
+begin
+
+	nomem_output : process(headerIn)
+		variable rxPortNr : portNrWrapper;
+	begin
+		-- default assignments
+		selected <= (others => '0');
+		dataValid <= '0';
+		selectedRxPort <= (others => '-');
+		selectedAddr <= dontCareAddr;
+
+		rxPortNr := selectHeader(headerIn);
+		if rxPortNr /= portNrUndefined then
+			selected(wrappedPortNrToInteger(rxPortNr)) <= '1';
+			dataValid <= '1';
+			selectedRxPort <= toPortNr(rxPortNr);
+			selectedAddr <= headerIn(wrappedPortNrToInteger(rxPortNr)).addr;
+		end if;
+
+	end process nomem_output;
+end architecture rtl;

pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/intTxPortSelect.vhd

@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.switchPkg.all;
+
+entity intTxPortSelect is
+	generic(
+		txPortNr			: portNr
+	);
+	port (
+		rxPortNrIn 			: in portNr;
+		rxPortNrOut			: out portNr;
+
+		txPortIdle			: in std_logic;
+		txPortWriteEnable	: out std_logic;
+
+		txFifoReadEnable	: out std_logic;
+		txFifoEmpty			: in std_logic;
+
+		txPortNrOut			: out portNr;
+		rxPortWriteEnable	: out std_logic_vector(numPorts-1 downto 0)
+	);
+end entity intTxPortSelect;
+
+architecture rtl of intTxPortSelect is
+
+begin
+
+	txPortNrOut <= txPortNr;
+	rxPortNrOut <= rxPortNrIn;
+
+	nomem_output:process(txPortIdle, txFifoEmpty, rxPortNrIn) is
+	begin
+		-- default assignments
+		txPortWriteEnable <= '0';
+		txFifoReadEnable <= '0';
+		rxPortWriteEnable <= (others => '0');
+
+		if txPortIdle = '1' and txFifoEmpty = '0' then
+			txPortWriteEnable <= '1';
+			txFifoReadEnable <= '1';
+			rxPortWriteEnable(portNrToInteger(rxPortNrIn)) <= '1';
+		end if;
+	end process nomem_output;
+
+end architecture rtl;