Changed included libraries from work to noc_switch_v1_00_a

rihuber · Mar 29, 2012 · bd3bbd3 · bd3bbd3
1 parent ea7bf8a
commit bd3bbd3
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Showing 14 changed files with 89 additions and 62 deletions.
diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/noc_switch.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/noc_switch.vhd
@@ -8,7 +8,7 @@ use noc_switch_v1_00_a.headerPkg.all;
 
 entity noc_switch is
 	generic (
-		globalAddr : integer
+		globalAddr : std_logic_vector(4 downto 0) := (others => '0')
 	);
   	port (
   		clk125					: in  std_logic;
@@ -34,11 +34,19 @@ entity noc_switch is
 		upstream1Full 			: out std_logic;
 		upstream1WriteClock 	: in  std_logic;
 
-		ringInputIn				: in  inputLinkInArray(numExtPorts-1 downto 0);
-		ringInputOut			: out inputLinkOutArray(numExtPorts-1 downto 0);
+		ringInputEmpty			: in std_logic_vector(numExtPorts-1 downto 0);
+		ringInputData			: in std_logic_vector((numExtPorts*(dataWidth+1))-1 downto 0);
+		ringInputReadEnable		: out std_logic_vector(numExtPorts-1 downto 0);
+
+		ringOutputReadEnable	: in std_logic_vector(numExtPorts-1 downto 0);
+		ringOutputData			: out std_logic_vector((numExtPorts*(dataWidth+1))-1 downto 0);
+		ringOutputEmpty			: out std_logic_vector(numExtPorts-1 downto 0)
+
+--		ringInputIn				: in  inputLinkInArray(numExtPorts-1 downto 0);
+--		ringInputOut			: out inputLinkOutArray(numExtPorts-1 downto 0);
 
-		ringOutputIn			: in  inputLinkOutArray(numExtPorts-1 downto 0);
-		ringOutputOut			: out inputLinkInArray(numExtPorts-1 downto 0)
+		--ringOutputIn			: in  inputLinkOutArray(numExtPorts-1 downto 0);
+		--ringOutputOut			: out inputLinkInArray(numExtPorts-1 downto 0)
   	);
 end noc_switch;
 
@@ -68,27 +76,30 @@ architecture rtl of noc_switch is
 	);
 	end component;
 
-	component interSwitchFifo
-		port (
-		rst: IN std_logic;
-		clk: IN std_logic;
-		din: IN std_logic_VECTOR(8 downto 0);
-		wr_en: IN std_logic;
-		rd_en: IN std_logic;
-		dout: OUT std_logic_VECTOR(8 downto 0);
-		full: OUT std_logic;
-		empty: OUT std_logic
-	);
-	end component;
+	COMPONENT interSwitchFifo
+	  PORT (
+	    clk : IN STD_LOGIC;
+	    rst : IN STD_LOGIC;
+	    din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+	    wr_en : IN STD_LOGIC;
+	    rd_en : IN STD_LOGIC;
+	    dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+	    full : OUT STD_LOGIC;
+	    empty : OUT STD_LOGIC
+	  );
+END COMPONENT;
 
 begin
 
 	-----------------------------------------------------------------
-	-- UPSTREAM FROM FUNCTIONAL BLOCK
+	-- INPUT FROM RING
 	-----------------------------------------------------------------
 
-	swInputLinksIn(numPorts-1 downto numIntPorts) <= ringInputIn;
-	ringInputOut <= swInputLinksOut(numPorts-1 downto numIntPorts);
+	ring_input_generate : for i in numPorts-1 downto numIntPorts generate
+		swInputLinksIn(i).empty <= ringInputEmpty(i-numIntPorts);
+		swInputLinksIn(i).data <= ringInputData((i-numIntPorts+1)*(dataWidth+1)-1 downto (i-numIntPorts)*(dataWidth+1));
+		ringInputReadEnable(i-numIntPorts) <= swInputLinksOut(i).readEnable;
+	end generate;
 
 
 	-----------------------------------------------------------------
@@ -145,9 +156,10 @@ begin
 	-----------------------------------------------------------------
 
 	generate_output_buffer_fifo: for i in numIntPorts to numPorts-1 generate	
-		outputBufferFifo : interSwitchFifo
+		outputBufferFifo : fbSwitchFifo
 			port map (
-				clk => clk125,
+				rd_clk => clk125,
+				wr_clk => clk125,
 				rst => reset,
 				din => swOutputLinksOut(i).data,
 				wr_en => swOutputLinksOut(i).writeEnable,
@@ -189,9 +201,11 @@ begin
 	-- OUTPUT TO RING
 	-----------------------------------------------------------------
 
-	ringOutputOut(numExtPorts-1 downto 0) <= outputBufferOut(numPorts-1 downto numIntPorts);
-	outputBufferIn(numPorts-1 downto numIntPorts) <= ringOutputIn;
-
+	ring_out_generate : for i in numPorts-1 downto numIntPorts generate
+		ringOutputEmpty(i-numIntPorts) <= outputBufferOut(i).empty;
+		ringOutputData((i-numIntPorts+1)*(dataWidth+1)-1 downto (i-numIntPorts)*(dataWidth+1)) <= outputBufferOut(i).data;
+		outputBufferIn(i).readEnable <= ringOutputReadEnable(i-numIntPorts);
+	end generate;
 
 	-----------------------------------------------------------------
 	-- DOWNSTREAM TO FUNCTIONAL BLOCK

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/header/headerDecoder.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/header/headerDecoder.vhd
@@ -2,7 +2,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.headerPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.headerPkg.all;
 
 entity headerDecoder is
 		port (

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/header/headerPkg.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/header/headerPkg.vhd
@@ -2,7 +2,8 @@ library IEEE;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.utilPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.utilPkg.all;
 
 package headerPkg is
 

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/extTxPortSelect.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/extTxPortSelect.vhd
@@ -2,7 +2,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity extTxPortSelect is
 	port (

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/headerFetch.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/headerFetch.vhd
@@ -1,7 +1,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.headerPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.headerPkg.all;
 
 entity headerFetch is
 	port (

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/headerSelect.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/headerSelect.vhd
@@ -2,9 +2,10 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.headerPkg.all;
-use work.utilPkg.all;
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.headerPkg.all;
+use noc_switch_v1_00_a.utilPkg.all;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity headerSelect is
 	port (

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/intTxPortSelect.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/intTxPortSelect.vhd
@@ -1,7 +1,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity intTxPortSelect is
 	generic(

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/router.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/router.vhd
@@ -1,8 +1,9 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.headerPkg.all;
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.headerPkg.all;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity router is
 	generic(
@@ -54,7 +55,7 @@ begin
 
 	headerFetchGenerate : for i in numPorts-1 downto 0 generate
 
-		headerFetchEntity: entity work.headerFetch
+		headerFetchEntity: entity noc_switch_v1_00_a.headerFetch
 			port map (
 				clk 			=> clk,
 				reset 			=> reset,
@@ -66,7 +67,7 @@ begin
 
 	end generate headerFetchGenerate;
 
-	headerSelectEntity: entity work.headerSelect
+	headerSelectEntity: entity noc_switch_v1_00_a.headerSelect
 		port map (
 			headerIn		=> headerFetch_headerOut,
 			selected		=> headerFetch_selected,
@@ -75,7 +76,7 @@ begin
 			selectedAddr	=> headerSelect_selectedAddr
 		);
 
-	txFifoSelectEntity: entity work.txFifoSelect
+	txFifoSelectEntity: entity noc_switch_v1_00_a.txFifoSelect
 		generic map (
 			globalAddress	=> globalAddress
 		)
@@ -87,7 +88,7 @@ begin
 
 	intTxFifoGenerate: for i in numIntPorts-1 downto 0 generate
 
-		intTxFifoEntity: entity work.txFifo
+		intTxFifoEntity: entity noc_switch_v1_00_a.txFifo
 			port map (
 				clk 		=> clk,
 				reset 		=> reset,
@@ -100,7 +101,7 @@ begin
 
 	end generate intTxFifoGenerate;
 
-	extTxFifoEntity: entity work.txFifo
+	extTxFifoEntity: entity noc_switch_v1_00_a.txFifo
 		port map (
 			clk 		=> clk,
 			reset 		=> reset,
@@ -113,7 +114,7 @@ begin
 
 	intTxPortSelectGenerate: for i in numIntPorts-1 downto 0 generate
 
-		intTxPortSelectEntity: entity work.intTxPortSelect
+		intTxPortSelectEntity: entity noc_switch_v1_00_a.intTxPortSelect
 			generic map (
 				txPortNr			=> integerToPortNr(i)
 			)
@@ -130,7 +131,7 @@ begin
 
 	end generate intTxPortSelectGenerate;
 
-	extTxPortSelectEntity: entity work.extTxPortSelect
+	extTxPortSelectEntity: entity noc_switch_v1_00_a.extTxPortSelect
 		port map (
 			rxPortNrIn 			=> txFifo_rxPortNr(numIntPorts),
 			rxPortNrOut			=> txPortSelect_rxPortNr(numIntPorts),
@@ -144,7 +145,7 @@ begin
 
 	intTxPortGenerate: for i in numIntPorts-1 downto 0 generate
 
-		intTxPortEntity: entity work.txPort
+		intTxPortEntity: entity noc_switch_v1_00_a.txPort
 			port map(
 				clk			=> clk,
 				reset		=> reset,
@@ -159,7 +160,7 @@ begin
 
 	extTxPortGenerate: for i in numExtPorts-1 downto 0 generate
 
-		extTxPortEntity: entity work.txPort
+		extTxPortEntity: entity noc_switch_v1_00_a.txPort
 			port map(
 				clk			=> clk,
 				reset		=> reset,
@@ -174,7 +175,7 @@ begin
 
 	rxPortGenerate: for i in numPorts-1 downto 0 generate
 
-		rxPortEntity:entity work.rxPort
+		rxPortEntity:entity noc_switch_v1_00_a.rxPort
 			port map(
 				clk	 		=> clk,
 				reset 		=> reset,

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/rxPort.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/rxPort.vhd
@@ -1,7 +1,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity rxPort is
 	port (

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/txFifo.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/txFifo.vhd
@@ -2,9 +2,10 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.utilPkg.all;
-use work.headerPkg.all;
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.utilPkg.all;
+use noc_switch_v1_00_a.headerPkg.all;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity txFifo is
 	port (

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/txFifoSelect.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/txFifoSelect.vhd
@@ -2,9 +2,10 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.utilPkg.all;
-use work.headerPkg.all;
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.utilPkg.all;
+use noc_switch_v1_00_a.headerPkg.all;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity txFifoSelect is
 	generic(

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/txPort.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/router/txPort.vhd
@@ -1,7 +1,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.switchPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.switchPkg.all;
 
 entity txPort is
 	port (

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/switch.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/switch.vhd
@@ -1,8 +1,9 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.switchPkg.all;
-use work.headerPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.switchPkg.all;
+use noc_switch_v1_00_a.headerPkg.all;
 
 entity switch is
 	generic(
@@ -40,7 +41,7 @@ begin
 
 	headerDetectorGenerate: for i in numPorts-1 downto 0 generate
 
-		headerDetectorEntity : entity work.headerDetector
+		headerDetectorEntity : entity noc_switch_v1_00_a.headerDetector
 			port map(
 				clk 		=> clk,
 				reset 		=> reset,
@@ -54,7 +55,7 @@ begin
 
 	headerDecoderGenerate: for i in numPorts-1 downto 0 generate
 
-		headerDecoderEntity : entity work.headerDecoder
+		headerDecoderEntity : entity noc_switch_v1_00_a.headerDecoder
 			port map(
 				data		=> inputLinksIn(i).data(dataWidth-1 downto 0),
 				destAddr	=> router_routingRequest(i).addr,
@@ -67,7 +68,7 @@ begin
 
 		invertedInputLinksInEmpty(i) <= not inputLinksIn(i).empty;
 
-		rxEndOfPacketDetectorEntity: entity work.endOfPacketDetector
+		rxEndOfPacketDetectorEntity: entity noc_switch_v1_00_a.endOfPacketDetector
 			port map(
 				dataValid	=> invertedInputLinksInEmpty(i),
 				flag		=> inputLinksIn(i).data(dataWidth),
@@ -77,7 +78,7 @@ begin
 
 		invertedOutputLinksInFull(i) <= not outputLinksIn(i).full;
 
-		txEndOfPacketDetectorEntity: entity work.endOfPacketDetector
+		txEndOfPacketDetectorEntity: entity noc_switch_v1_00_a.endOfPacketDetector
 			port map(
 				dataValid	=> invertedOutputLinksInFull(i),
 				flag		=> outputLinksOutMuxOutput(i).data(dataWidth),
@@ -87,7 +88,7 @@ begin
 
 	end generate endOfPacketDetectorGenerate;
 
-	routerEntity: entity work.router
+	routerEntity: entity noc_switch_v1_00_a.router
 		generic map (
 			globalAddress	=> globalAddress
 		)

diff --git a/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/switchPkg.vhd b/pcores/noc_switch_v1_00_a/hdl/vhdl/switch/switchPkg.vhd
@@ -2,8 +2,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.utilPkg.all;
-use work.headerPkg.all;
+library noc_switch_v1_00_a;
+use noc_switch_v1_00_a.utilPkg.all;
+use noc_switch_v1_00_a.headerPkg.all;
 
 package switchPkg is