Merge pull request #470 from riscv-boom/rc-retile

Update Tile instantiation for RC bump

.circleci/build-toolchains.sh

@@ -28,5 +28,5 @@ if [ ! -d "$HOME/$1-install" ]; then
     cd $HOME
 
     # init all submodules including the tools (doesn't use CI_MAKE_PROC due to mem. constraints)
-    CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=$CI_MAKE_PROC $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1
+    CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=4 $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1
 fi

.circleci/do-rtl-build.sh

@@ -47,12 +47,12 @@ else
 fi
 
 # enter the verilator directory and build the specific config on remote server
-run "make -C $REMOTE_SIM_DIR clean"
 run "export RISCV=\"$TOOLS_DIR\"; \
      export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
      export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
      export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
      export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
+     make -C $REMOTE_SIM_DIR clean; \
      make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
 

CHIPYARD.hash

@@ -1 +1 @@
-6f1a53a2f3e43c8444a308e002a611fcfb995bcc
+a1cc62b85aa4a53c5c69c1e9114ab0aafed8446f