Use Option for PTW instantiation

riscv-boom · Feb 23, 2019 · 21a89c4 · 21a89c4
1 parent e9c3375
commit 21a89c4
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Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
@@ -194,7 +194,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer)
   core.io.ptw := DontCare
   if (usingPTW)
   {
-    core.io.ptw <> ptw.io.dpath
+    core.io.ptw <> ptw.get.io.dpath
   }
   core.io.rocc := DontCare
   core.io.fpu := DontCare
@@ -226,7 +226,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer)
   core.io.ptw_tlb := DontCare
   if (usingPTW)
   {
-    ptw.io.requestor <> ptwPorts
+    ptw.get.io.requestor <> ptwPorts
   }
   val frontendStr = outer.frontend.module.toString
   ElaborationArtefacts.add(

diff --git a/src/main/scala/lsu/types.scala b/src/main/scala/lsu/types.scala
@@ -11,6 +11,7 @@ import scala.collection.mutable.ListBuffer
 
 import chisel3._
 
+import freechips.rocketchip.util._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{AddressSet, LazyModule}
 import freechips.rocketchip.rocket.{DCache, HellaCache, HellaCacheArbiter, HellaCacheIO, NonBlockingDCache, PTW}
@@ -68,10 +69,10 @@ trait CanHaveBoomPTWModule extends HasBoomHellaCacheModule
 {
   val outer: CanHaveBoomPTW
   val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
-  val ptw = if (outer.usingPTW) Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) else null
+  val ptw: Option[PTW] = (outer.usingPTW).option(Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)))
   if (outer.usingPTW)
   {
-    dcachePorts += ptw.io.mem
+    dcachePorts += ptw.get.io.mem
   }
 }