Add support for unified MEM + INT issue queues, test SmallRV32Unified…

… instead of SmallRV32 config
riscv-boom · Feb 6, 2019 · 330dfce · 330dfce
1 parent 46fd0e1
commit 330dfce
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Showing 7 changed files with 46 additions and 29 deletions.
diff --git a/.circleci/config.yml b/.circleci/config.yml
@@ -102,7 +102,7 @@ jobs:
                 paths:
                     - "/home/riscvuser/boom-template"
 
-    prepare-smallrv32boomconfig:
+    prepare-smallrv32unifiedboomconfig:
         docker:
             - image: riscvboom/riscvboom-images:0.0.5
         environment:
@@ -128,12 +128,12 @@ jobs:
                     - boom-template-with-verilator-v5-{{ checksum "../boom-template.hash" }}
 
             - run:
-                name: Building SmallRV32BoomConfig using Verilator
-                command: .circleci/do-rtl-build.sh SmallRV32BoomConfig
+                name: Building SmallRV32UnifiedBoomConfig using Verilator
+                command: .circleci/do-rtl-build.sh SmallRV32UnifiedBoomConfig
                 no_output_timeout: 120m
 
             - save_cache:
-                key: boom-template-smallrv32boomconfig-{{ .Branch }}-{{ .Revision }}
+                key: boom-template-smallrv32unifiedboomconfig-{{ .Branch }}-{{ .Revision }}
                 paths:
                     - "/home/riscvuser/boom-template"
 
@@ -381,7 +381,7 @@ jobs:
                 no_output_timeout: 30m
 
     # No benchmark tests because those are rv64gc
-    smallrv32boomconfig-run-assembly-tests:
+    smallrv32unifiedboomconfig-run-assembly-tests:
         docker:
             - image: riscvboom/riscvboom-images:0.0.5
         environment:
@@ -399,10 +399,10 @@ jobs:
                     - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
             - restore_cache:
                 keys:
-                    - boom-template-smallrv32boomconfig-{{ .Branch }}-{{ .Revision }}
+                    - boom-template-smallrv32unifiedboomconfig-{{ .Branch }}-{{ .Revision }}
             - run:
-                name: Run SmallRV32BoomConfig assembly tests
-                command: make run-asm-tests -C ../boom-template/verisim CONFIG=SmallRV32BoomConfig
+                name: Run SmallRV32UnifiedBoomConfig assembly tests
+                command: make run-asm-tests -C ../boom-template/verisim CONFIG=SmallRV32UnifiedBoomConfig
                 no_output_timeout: 300m
 
     smallboomconfig-run-benchmark-tests:
@@ -656,7 +656,7 @@ workflows:
             - prepare-boomconfig:
                 requires:
                     - prepare-build-environment
-            - prepare-smallrv32boomconfig:
+            - prepare-smallrv32unifiedboomconfig:
                 requires:
                     - prepare-build-environment
             - prepare-smallboomconfig:
@@ -682,10 +682,10 @@ workflows:
                 requires:
                     - prepare-boomconfig
 
-            # Run the SmallRV32BoomConfig tests
-            - smallrv32boomconfig-run-assembly-tests:
+            # Run the SmallRV32UnifiedBoomConfig tests
+            - smallrv32unifiedboomconfig-run-assembly-tests:
                 requires:
-                    - prepare-smallrv32boomconfig
+                    - prepare-smallrv32unifiedboomconfig
 
             # Run the SmallBoomConfig tests
             - smallboomconfig-run-csmith-tests:

diff --git a/src/main/scala/common/configs.scala b/src/main/scala/common/configs.scala
@@ -64,6 +64,13 @@ class WithBoomRV32 extends Config((site, here, up) => {
   }
 })
 
+class WithUnifiedMemIntIQs extends Config((site, here, up) => {
+   case BoomTilesKey => up(BoomTilesKey, site) map { r =>
+      r.copy(core = r.core.copy(
+         issueParams = r.core.issueParams.filter(_.iqType != IQT_MEM.litValue)
+      ))
+   }
+})
 
 
 class WithoutBoomFPU extends Config((site, here, up) => {
@@ -91,6 +98,7 @@ class WithRVC extends Config((site, here, up) => {
          useCompressed = true))}
 })
 
+
 // Small BOOM! Try to be fast to compile and easier to debug.
 class WithSmallBooms extends Config((site, here, up) => {
    case BoomTilesKey => up(BoomTilesKey, site) map { r =>r.copy(

diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -771,7 +771,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    issue_units.map(_.io.flush_pipeline := rob.io.flush.valid)
 
    // Load-hit Misspeculations
-   require (issue_units.count(_.iqType == IQT_MEM.litValue) == 1)
+   require (issue_units.count(_.iqType == IQT_MEM.litValue) == 1 || usingUnifiedMemIntIQs)
    val mem_iq = issue_units.mem_iq
 
    require (mem_iq.issue_width == 1)
@@ -791,7 +791,6 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
 
    // Share the memory port with other long latency operations.
    val mem_unit = exe_units.memory_unit
-   require (mem_unit.writes_ll_irf)
    val mem_resp = mem_unit.io.ll_iresp
 
    when (RegNext(!sxt_ldMiss) && RegNext(RegNext(lsu.io.mem_ldSpecWakeup.valid)) &&
@@ -1037,9 +1036,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
       }
    }
    require(w_cnt == iregfile.io.write_ports.length)
-
-   ll_wbarb.io.in(0).valid := mem_resp.valid && mem_resp.bits.uop.ctrl.rf_wen && mem_resp.bits.uop.dst_rtype === RT_FIX
-   ll_wbarb.io.in(0).bits  := mem_resp.bits
+   ll_wbarb.io.in(0) <> mem_resp
    assert (ll_wbarb.io.in(0).ready) // never backpressure the memory unit.
 
    if (usingFPU)
@@ -1087,7 +1084,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
          val resp   = eu.io.iresp
          val wb_uop = resp.bits.uop
          val data   = resp.bits.data
-         assert(!eu.has_mem)
+
          rob.io.wb_resps(cnt).valid := resp.valid && !(wb_uop.is_store && !wb_uop.is_amo)
          rob.io.wb_resps(cnt).bits  <> resp.bits
          rob.io.debug_wb_valids(cnt) := resp.valid && wb_uop.ctrl.rf_wen && wb_uop.dst_rtype === RT_FIX

diff --git a/src/main/scala/exu/decode.scala b/src/main/scala/exu/decode.scala
@@ -443,6 +443,8 @@ class DecodeUnit(implicit p: Parameters) extends BoomModule()(p)
 
    uop.uopc       := cs.uopc
    uop.iqtype     := cs.iqtype
+   if (usingUnifiedMemIntIQs)
+      when (cs.iqtype === IQT_MEM) { uop.iqtype := IQT_INT }
    uop.fu_code    := cs.fu_code
 
    // x-registers placed in 0-31, f-registers placed in 32-63.

diff --git a/src/main/scala/exu/execute.scala b/src/main/scala/exu/execute.scala
@@ -141,7 +141,8 @@ class ALUExeUnit(
       reads_irf  = true,
       writes_irf = has_alu || has_mul || has_div,
       writes_ll_irf = has_mem,
-      writes_ll_frf = has_ifpu || has_mem, 
+      writes_ll_frf = (has_ifpu || has_mem)
+         && p(tile.TileKey).core.fpu != None,
       num_bypass_stages =
          if (has_alu && has_mul) 3 //TODO XXX p(tile.TileKey).core.imulLatency
          else if (has_alu) 1 else 0,
@@ -340,6 +341,7 @@ class ALUExeUnit(
       // Hook up loads to the response
       io.ll_iresp.valid                 := RegNext(memresp_val
                                                 && !IsKilledByBranch(io.brinfo, memresp_uop)
+                                                && memresp_rf_wen
                                                 && memresp_uop.dst_rtype === RT_FIX)
       io.ll_iresp.bits.uop              := RegNext(memresp_uop)
       io.ll_iresp.bits.uop.ctrl.rf_wen  := RegNext(memresp_rf_wen)
@@ -349,8 +351,9 @@ class ALUExeUnit(
       {
          require(!has_alu, "Don't support this yet")
          io.ll_fresp.valid                 := RegNext(memresp_val
-            && !IsKilledByBranch(io.brinfo, memresp_uop)
-            && memresp_uop.dst_rtype === RT_FLT)
+                                                   && !IsKilledByBranch(io.brinfo, memresp_uop)
+                                                   && memresp_rf_wen
+                                                   && memresp_uop.dst_rtype === RT_FLT)
          io.ll_fresp.bits.uop              := RegNext(memresp_uop)
          io.ll_fresp.bits.uop.ctrl.rf_wen  := RegNext(memresp_rf_wen)
          io.ll_fresp.bits.data             := RegNext(memresp_data)

diff --git a/src/main/scala/exu/execution_units.scala b/src/main/scala/exu/execution_units.scala
@@ -108,21 +108,26 @@ class ExecutionUnits(fpu: Boolean)(implicit val p: Parameters) extends HasBoomCo
    if (!fpu)
    {
       val int_width = issueParams.find(_.iqType == IQT_INT.litValue).get.issueWidth
-      val memExeUnit = Module(new ALUExeUnit(
-         has_alu = false,
-         has_mem = true))
 
-      memExeUnit.io.status := DontCare
-      memExeUnit.io.get_ftq_pc := DontCare
-      memExeUnit.io.ll_iresp.ready := DontCare
+      if (!usingUnifiedMemIntIQs)
+      {
+         val memExeUnit = Module(new ALUExeUnit(
+            has_alu = false,
+            has_mem = true))
 
-      exe_units += memExeUnit
+         memExeUnit.io.status := DontCare
+         memExeUnit.io.get_ftq_pc := DontCare
+         memExeUnit.io.ll_iresp.ready := DontCare
+
+         exe_units += memExeUnit
+      }
 
       val aluExeUnit = Module(new ALUExeUnit(has_br_unit      = true
          , shares_csr_wport = true
          , has_mul          = true
          , has_div          = true
          , has_ifpu         = usingFPU
+         , has_mem          = usingUnifiedMemIntIQs
       ))
 
       aluExeUnit.io.lsu_io := DontCare

diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
@@ -125,17 +125,19 @@ class TracedSmallBoomConfig extends Config(
    new freechips.rocketchip.system.BaseConfig)
 
 //RV32IMAC TODO: Support FP
-class SmallRV32BoomConfig extends Config(
+class SmallRV32UnifiedBoomConfig extends Config(
    new WithBoomRV32 ++
    new WithRVC ++
    new WithoutBoomFPU ++
+   new WithUnifiedMemIntIQs ++
    new WithSmallBooms ++
    new DefaultBoomConfig ++
    new WithNBoomCores(1) ++
    new WithoutTLMonitors ++
    new freechips.rocketchip.system.BaseConfig)
 
 
+
 // Allow for some number N BOOM cores.
 class WithNBoomCores(n: Int) extends Config((site, here, up) => {
   case BoomTilesKey => {