Fixed prev_is_half

prev_is_half could be set in a configuration without RVC
riscv-boom · Feb 27, 2019 · 3fa27cf · 3fa27cf
1 parent c3858e9
commit 3fa27cf
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/ifu/fetch-control-unit.scala b/src/main/scala/ifu/fetch-control-unit.scala
@@ -371,8 +371,8 @@ class FetchControlUnit(fetch_width: Int)(implicit p: Parameters) extends BoomMod
    {
       val last_idx  = Mux(inLastChunk(f3_fetch_bundle.pc) && icIsBanked.B,
                           (fetchWidth/2-1).U, (fetchWidth-1).U)
-      prev_is_half := (
-         !(f3_valid_mask(last_idx-1.U) && f3_fetch_bundle.insts(last_idx-1.U)(1,0) === 3.U)
+      prev_is_half := (usingCompressed.B
+      && !(f3_valid_mask(last_idx-1.U) && f3_fetch_bundle.insts(last_idx-1.U)(1,0) === 3.U)
       && !f3_kill_mask(last_idx)
       && f3_btb_mask(last_idx)
       && f3_bpd_mask(last_idx)