Fix RoCC PTW port connection

riscv-boom · Mar 20, 2023 · 47c6f9c · 47c6f9c
1 parent 21d5334
commit 47c6f9c
Showing 1 changed file with 6 additions and 6 deletions.
diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
@@ -176,12 +176,6 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
 
   //fpuOpt foreach { fpu => core.io.fpu <> fpu.io } RocketFpu - not needed in boom
   core.io.rocc := DontCare
-
-  // PTW
-  val ptw  = Module(new PTW(ptwPorts.length)(outer.dcache.node.edges.out(0), outer.p))
-  core.io.ptw <> ptw.io.dpath
-  ptw.io.requestor <> ptwPorts.toSeq
-  hellaCachePorts += ptw.io.mem
 
   // RoCC
   if (outer.roccs.size > 0) {
@@ -230,6 +224,12 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
     core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_||_)
   }
 
+  // PTW
+  val ptw  = Module(new PTW(ptwPorts.length)(outer.dcache.node.edges.out(0), outer.p))
+  core.io.ptw <> ptw.io.dpath
+  ptw.io.requestor <> ptwPorts.toSeq
+  ptw.io.mem +=: hellaCachePorts
+
    // LSU IO
   val hellaCacheArb = Module(new HellaCacheArbiter(hellaCachePorts.length)(outer.p))
   hellaCacheArb.io.requestor <> hellaCachePorts.toSeq