Merge pull request #379 from riscv-boom/no_system

Move system/subsystem/configs to chipyard
riscv-boom · Aug 30, 2019 · 527c7ba · 527c7ba
2 parents ac28f02 + 7b68d74
commit 527c7ba
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Showing 7 changed files with 42 additions and 387 deletions.
diff --git a/.circleci/config.yml b/.circleci/config.yml
@@ -170,7 +170,7 @@ jobs:
             - run:
                 name: Building MegaBoomConfig using Verilator
                 command: .circleci/do-rtl-build.sh megaboom
-                no_output_timeout: 240m
+                no_output_timeout: 120m
             - save_cache:
                 key: megaboomconfig-{{ .Branch }}-{{ .Revision }}
                 paths:

diff --git a/CHIPYARD.hash b/CHIPYARD.hash
@@ -1 +1 @@
-9844fcf43bcfc3590891971934ebdfcf29bad00d
+71b3d7e1e688267d175cdced81307c662fe11f03
diff --git a/src/main/scala/common/config-mixins.scala b/src/main/scala/common/config-mixins.scala
@@ -8,8 +8,8 @@ package boom.common
 import chisel3._
 import chisel3.util.{log2Up}
 
-import freechips.rocketchip.config.{Parameters, Config}
-import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey}
+import freechips.rocketchip.config.{Parameters, Config, Field}
+import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams}
 import freechips.rocketchip.devices.tilelink.{BootROMParams}
 import freechips.rocketchip.diplomacy.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing}
 import freechips.rocketchip.rocket._
@@ -19,29 +19,14 @@ import boom.ifu._
 import boom.bpu._
 import boom.exu._
 import boom.lsu._
-import boom.system.{BoomTilesKey, BoomCrossingKey}
+
+case object BoomTilesKey extends Field[Seq[BoomTileParams]](Nil)
+case object BoomCrossingKey extends Field[Seq[RocketCrossingParams]](List(RocketCrossingParams()))
 
 // ---------------------
 // BOOM Configs
 // ---------------------
 
-/**
- * Baseline BOOM configuration.
- */
-class BaseBoomConfig extends Config((site, here, up) => {
-  // Top-Level
-  case XLen => 64
-
-  // Specify things which are typically common between core configs.
-  case BoomTilesKey => up(BoomTilesKey, site) map { b => b.copy(
-    core = b.core.copy(
-      fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true)))
-  )}
-
-  // Make sure there are enough hart bits to support multiple cores
-  case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
-})
-
 /**
  * Enables RV32 version of the core
  */
@@ -68,10 +53,14 @@ class WithUnifiedMemIntIQs extends Config((site, here, up) => {
 })
 
 /**
-  * Adds a boot ROM.
-  */
-class WithBootROM extends Config((site, here, up) => {
-  case BootROMParams => BootROMParams(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
+ * Disable support for C-extension (RVC)
+ */
+class WithoutBoomRVC extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey, site) map { b =>
+    b.copy(core = b.core.copy(
+      fetchWidth = b.core.fetchWidth / 2,
+      useCompressed = false))
+   }
 })
 
 /**
@@ -112,16 +101,6 @@ class WithTrace extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey, site) map { b => b.copy(trace = true) }
 })
 
-/**
- * Enable RVC
- */
-class WithRVC extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey, site) map { b => b.copy(
-    core = b.core.copy(
-      fetchWidth = b.core.fetchWidth * 2,
-      useCompressed = true))}
-})
-
 /**
  * Create multiple copies of a BOOM tile (and thus a core).
  * Override with the default mixins to control all params of the tiles.
@@ -131,36 +110,13 @@ class WithRVC extends Config((site, here, up) => {
  */
 class WithNBoomCores(n: Int) extends Config(
   new WithSmallBooms ++
-  new BaseBoomConfig ++
   new Config((site, here, up) => {
     case BoomTilesKey => {
       List.tabulate(n)(i => BoomTileParams(hartId = i))
     }
   })
 )
 
-/**
- * This sets the ECC for the L1 instruction cache.
- *
- * @param tecc ...
- * @param decc ...
- */
-class WithL1IECC(tecc: String, decc: String) extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey, site) map { r =>
-    r.copy(icache = r.icache.map(_.copy(tagECC = Some(tecc), dataECC = Some(decc)))) }
-})
-
-/**
- * This sets the ECC for the L1 data cache.
- *
- * @param tecc ...
- * @param decc ...
- */
-class WithL1DECC(tecc: String, decc: String) extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey, site) map { r =>
-    r.copy(dcache = r.dcache.map(_.copy(tagECC = Some(tecc), dataECC = Some(decc)))) }
-})
-
 /**
  * Class to renumber BOOM + Rocket harts so that there are no overlapped harts
  * This mixin assumes Rocket tiles are numbered before BOOM tiles
@@ -210,7 +166,8 @@ class WithRationalBoomTiles extends Config((site, here, up) => {
 class WithSmallBooms extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey, site) map { b => b.copy(
     core = b.core.copy(
-      fetchWidth = 2,
+      fetchWidth = 4,
+      useCompressed = true,
       decodeWidth = 1,
       numRobEntries = 32,
       issueParams = Seq(
@@ -230,12 +187,15 @@ class WithSmallBooms extends Config((site, here, up) => {
       gshare = Some(GShareParameters(historyLength=11, numSets=2048)),
       tage = None,
       bpdRandom = None,
-      nPerfCounters = 2),
+      nPerfCounters = 2,
+      fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))),
     dcache = Some(DCacheParams(rowBits = site(SystemBusKey).beatBits,
                                nSets=64, nWays=4, nMSHRs=2, nTLBEntries=8)),
     icache = Some(ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, fetchBytes=2*4))
-    )}
+  )}
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
+  case XLen => 64
+  case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
 })
 
 /**
@@ -244,7 +204,8 @@ class WithSmallBooms extends Config((site, here, up) => {
 class WithMediumBooms extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey, site) map { b => b.copy(
     core = b.core.copy(
-      fetchWidth = 2,
+      fetchWidth = 4,
+      useCompressed = true,
       decodeWidth = 2,
       numRobEntries = 64,
       issueParams = Seq(
@@ -271,6 +232,9 @@ class WithMediumBooms extends Config((site, here, up) => {
     icache = Some(ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, fetchBytes=2*4))
     )}
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
+  case XLen => 64
+  case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
+
 })
 
 /**
@@ -279,7 +243,8 @@ class WithMediumBooms extends Config((site, here, up) => {
 class WithLargeBooms extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey, site) map { b => b.copy(
     core = b.core.copy(
-      fetchWidth = 4,
+      fetchWidth = 8,
+      useCompressed = true,
       decodeWidth = 3,
       numRobEntries = 96,
       issueParams = Seq(
@@ -297,12 +262,15 @@ class WithLargeBooms extends Config((site, here, up) => {
       bpdBaseOnly = None,
       gshare = Some(GShareParameters(historyLength=23, numSets=4096)),
       tage = None,
-      bpdRandom = None),
+      bpdRandom = None,
+      fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))),
     dcache = Some(DCacheParams(rowBits = site(SystemBusKey).beatBytes*8,
                                nSets=64, nWays=8, nMSHRs=4, nTLBEntries=16)),
     icache = Some(ICacheParams(fetchBytes = 4*4, rowBits = site(SystemBusKey).beatBytes*8, nSets=64, nWays=8))
-    )}
+  )}
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16)
+  case XLen => 64
+  case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
 })
 
 /**
@@ -311,7 +279,8 @@ class WithLargeBooms extends Config((site, here, up) => {
 class WithMegaBooms extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey, site) map { b => b.copy(
     core = b.core.copy(
-      fetchWidth = 4,
+      fetchWidth = 8,
+      useCompressed = true,
       decodeWidth = 4,
       numRobEntries = 128,
       issueParams = Seq(
@@ -329,10 +298,13 @@ class WithMegaBooms extends Config((site, here, up) => {
       bpdBaseOnly = None,
       gshare = Some(GShareParameters(historyLength=23, numSets=4096)),
       tage = None,
-      bpdRandom = None),
+      bpdRandom = None,
+      fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))),
     dcache = Some(DCacheParams(rowBits = site(SystemBusKey).beatBytes*8,
                                nSets=64, nWays=8, nMSHRs=8, nTLBEntries=32)),
     icache = Some(ICacheParams(fetchBytes = 4*4, rowBits = site(SystemBusKey).beatBytes*8, nSets=64, nWays=8))
-    )}
+  )}
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16)
+  case XLen => 64
+  case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
 })
diff --git a/src/main/scala/common/configs.scala b/src/main/scala/common/configs.scala
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -39,7 +39,7 @@ import freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle}
 
 import boom.common._
 import boom.exu.FUConstants._
-import boom.system.BoomTilesKey
+import boom.common.BoomTilesKey
 import boom.util.{RobTypeToChars, BoolToChar, GetNewUopAndBrMask, Sext, WrapInc, BoomCoreStringPrefix}
 
 /**