icache: switch dataArrays' size to ramDepth (#619)

Co-authored-by: lijue <lijue@pku.edu.cn>
riscv-boom · Jan 4, 2023 · 570d135 · 570d135
1 parent 426bcf9
commit 570d135
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/src/main/scala/ifu/icache.scala b/src/main/scala/ifu/icache.scala
@@ -195,7 +195,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
       DescribedSRAM(
         name = s"dataArrayWay_${x}",
         desc = "ICache Data Array",
-        size = nSets * refillCycles,
+        size = ramDepth,
         data = UInt((wordBits).W)
       )
     }
@@ -205,14 +205,14 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
       DescribedSRAM(
         name = s"dataArrayB0Way_${x}",
         desc = "ICache Data Array",
-        size = nSets * refillCycles,
+        size = ramDepth,
         data = UInt((wordBits/nBanks).W)
       )} ++
     (0 until nWays).map { x =>
       DescribedSRAM(
         name = s"dataArrayB1Way_${x}",
         desc = "ICache Data Array",
-        size = nSets * refillCycles,
+        size = ramDepth,
         data = UInt((wordBits/nBanks).W)
       )}
   }