Merge pull request #422 from riscv-boom/rc-bump-aug-2019

Fixes for rocket-chip bump
riscv-boom · Dec 12, 2019 · 63b430b · 63b430b
2 parents c9fa26d + 0c059c1
commit 63b430b
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Showing 15 changed files with 57 additions and 31 deletions.
diff --git a/CHIPYARD.hash b/CHIPYARD.hash
@@ -1 +1 @@
-2f3ac85c2ae0a679cdd900df55dbf7f1998f638c
+542b2a6e6e121a41f307b61336fa678eb0a45a1c
diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
@@ -188,7 +188,7 @@ class BoomTile(
   tlMasterXbar.node := frontend.masterNode
 
   private val deviceOpt = None
-  val iCacheLogicalTreeNode = new ICacheLogicalTreeNode(deviceOpt, tileParams.icache.get)
+  val iCacheLogicalTreeNode = new BoomICacheLogicalTreeNode(frontend.icache, deviceOpt, tileParams.icache.get)
 
   // ROCC
   val roccs = p(BuildRoCC).map(_(p))

diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -32,7 +32,6 @@ import java.nio.file.{Paths}
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.dontTouch
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.Instructions._
@@ -1301,7 +1300,7 @@ class BoomCore(implicit p: Parameters) extends BoomModule
         val mmioStart = "0x" + f"${bootromParams.address + bootromParams.size}%X"
         val mmioEnd = "0x" + f"${extMemParams.master.base}%X"
         val plicBase = "0x" + f"${plicParams.baseAddress}%X"
-        val plicSize = "0x" + f"${PLICConsts.size}%X"
+        val plicSize = "0x" + f"${PLICConsts.size(plicParams.maxHarts)}%X"
         val clintBase = "0x" + f"${clintParams.baseAddress}%X"
         val clintSize = "0x" + f"${CLINTConsts.size}%X"
         val memSize = "0x" + f"${extMemParams.master.size}%X"

diff --git a/src/main/scala/exu/execution-units/rocc.scala b/src/main/scala/exu/execution-units/rocc.scala
@@ -14,7 +14,6 @@ package boom.exu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.dontTouch
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.tile.{RoCCCoreIO, RoCCInstruction}

diff --git a/src/main/scala/ifu/fetch-buffer.scala b/src/main/scala/ifu/fetch-buffer.scala
@@ -15,8 +15,6 @@ package boom.ifu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{dontTouch}
-import chisel3.core.{DontCare}
 
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.rocket.{MStatus, BP, BreakpointUnit}

diff --git a/src/main/scala/ifu/fetch-control-unit.scala b/src/main/scala/ifu/fetch-control-unit.scala
@@ -23,8 +23,7 @@ package boom.ifu
 
 import chisel3._
 import chisel3.util._
-import chisel3.core.{withReset, DontCare}
-import chisel3.experimental.{dontTouch}
+import chisel3.core.{withReset}
 
 import freechips.rocketchip.rocket.{MStatus, BP}
 import freechips.rocketchip.config.{Parameters}

diff --git a/src/main/scala/ifu/fetch-monitor.scala b/src/main/scala/ifu/fetch-monitor.scala
@@ -13,7 +13,6 @@ package boom.ifu
 
 import chisel3._
 import chisel3.util._
-import chisel3.core.{DontCare}
 
 import freechips.rocketchip.config.{Parameters}
 

diff --git a/src/main/scala/ifu/fetch-target-queue.scala b/src/main/scala/ifu/fetch-target-queue.scala
@@ -18,8 +18,6 @@ package boom.ifu
 
 import chisel3._
 import chisel3.util._
-import chisel3.core.{DontCare}
-import chisel3.experimental.{dontTouch}
 
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{Str}

diff --git a/src/main/scala/ifu/frontend.scala b/src/main/scala/ifu/frontend.scala
@@ -24,7 +24,6 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{ICacheLogicalTreeNode}
 
 import boom.bpu._
 import boom.common._

diff --git a/src/main/scala/ifu/icache.scala b/src/main/scala/ifu/icache.scala
@@ -14,7 +14,6 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 import chisel3.internal.sourceinfo.{SourceInfo}
-import chisel3.experimental.{dontTouch}
 import chisel3.experimental.{chiselName}
 
 import freechips.rocketchip.config.{Parameters}
@@ -25,6 +24,9 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
 import freechips.rocketchip.rocket.{HasL1ICacheParameters, ICacheParams, ICacheErrors, ICacheReq}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode}
+import freechips.rocketchip.diplomaticobjectmodel.DiplomaticObjectModelAddressing
+import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMICache, OMECC}
 
 import boom.common._
 import boom.util.{BoomCoreStringPrefix}
@@ -68,6 +70,26 @@ class ICache(
       beatBytes = wordBytes,
       minLatency = 1)})
 }
+class BoomICacheLogicalTreeNode(icache: ICache, deviceOpt: Option[SimpleDevice], params: ICacheParams) extends LogicalTreeNode(() => deviceOpt) {
+  override def getOMComponents(resourceBindings: ResourceBindings, children: Seq[OMComponent] = Nil): Seq[OMComponent] = {
+    Seq(
+      OMICache(
+        memoryRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions("ITIM", resourceBindings),
+        interrupts = Nil,
+        nSets = params.nSets,
+        nWays = params.nWays,
+        blockSizeBytes = params.blockBytes,
+        dataMemorySizeBytes = params.nSets * params.nWays * params.blockBytes,
+        dataECC = params.dataECC.map(OMECC.fromString),
+        tagECC = params.tagECC.map(OMECC.fromString),
+        nTLBEntries = params.nTLBEntries,
+        maxTimSize = params.nSets * (params.nWays-1) * params.blockBytes,
+        memories = if(!icache.enableBlackBox) icache.module.asInstanceOf[ICacheModule].dataArrays.map(_._2)
+                   else Seq()
+      )
+    )
+  }
+}
 
 /**
  * IO Signals leaving the ICache
@@ -279,15 +301,37 @@ class ICacheModule(outer: ICache) extends ICacheBaseModule(outer)
     if (2*tl_out.d.bits.data.getWidth == wordBits) (nSets * refillCycles/2)
     else (nSets * refillCycles)
 
+  val dataArrays = if(cacheParams.fetchBytes <= 8)
+      // Use unbanked icache for narrow accesses.
+      (0 until nWays).map { x =>
+        DescribedSRAM(
+          name = s"dataArrayWay_${x}",
+          desc = "ICache Data Array",
+          size = nSets * refillCycles,
+          data = UInt(dECC.width(wordBits).W)
+        )
+      }
+    else
+      // Use two banks, interleaved.
+      (0 until nWays).map { x =>
+        DescribedSRAM(
+          name = s"dataArrayB0Way_${x}",
+          desc = "ICache Data Array",
+          size = nSets * refillCycles,
+          data = UInt(dECC.width(wordBits/nBanks).W)
+        )} ++
+      (0 until nWays).map { x =>
+        DescribedSRAM(
+          name = s"dataArrayB1Way_${x}",
+          desc = "ICache Data Array",
+          size = nSets * refillCycles,
+          data = UInt(dECC.width(wordBits/nBanks).W)
+        )}
+
   if (cacheParams.fetchBytes <= 8) {
     // Use unbanked icache for narrow accesses.
-    val dataArrays = (0 until nWays).map { x =>
-       SyncReadMem(nSets * refillCycles, UInt(dECC.width(wordBits).W)).suggestName(
-          "dataArrayWay_" + x.toString)
-    }
-
     s1_bankId := 0.U
-    for ((dataArray, i) <- dataArrays zipWithIndex) {
+    for ((dataArray, i) <- dataArrays.map(_._1) zipWithIndex) {
       def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
       val s0_ren = s0_valid || s0_slaveValid
 
@@ -305,13 +349,9 @@ class ICacheModule(outer: ICache) extends ICacheBaseModule(outer)
       s1_dout(i) := dataArray.read(mem_idx, !wen && s0_ren)
     }
   } else {
-    val dataArraysB0 = (0 until nWays).map { x =>
-      SyncReadMem(ramDepth, UInt(dECC.width(wordBits/nBanks).W)).suggestName(
-        "dataArrayB0Way_" + x.toString)}
-    val dataArraysB1 = (0 until nWays).map { x =>
-      SyncReadMem(ramDepth, UInt(dECC.width(wordBits/nBanks).W)).suggestName(
-        "dataArrayB1Way_" + x.toString)}
     // Use two banks, interleaved.
+    val dataArraysB0 = dataArrays.map(_._1).take(nWays)
+    val dataArraysB1 = dataArrays.map(_._1).drop(nWays)
     require (nBanks == 2)
 
     // Bank0 row's id wraps around if Bank1 is the starting bank.

diff --git a/src/main/scala/lsu/dcache.scala b/src/main/scala/lsu/dcache.scala
@@ -8,7 +8,6 @@ package boom.lsu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.dontTouch
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._

diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala
@@ -45,7 +45,6 @@ package boom.lsu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.dontTouch
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket

diff --git a/src/main/scala/lsu/mshrs.scala b/src/main/scala/lsu/mshrs.scala
@@ -8,7 +8,6 @@ package boom.lsu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.dontTouch
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._

diff --git a/src/main/scala/lsu/prefetcher.scala b/src/main/scala/lsu/prefetcher.scala
@@ -7,7 +7,6 @@ package boom.lsu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.dontTouch
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._

diff --git a/src/main/scala/lsu/tlb.scala b/src/main/scala/lsu/tlb.scala
@@ -2,7 +2,6 @@ package boom.lsu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.dontTouch
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket._