Merge pull request #448 from riscv-boom/release_fix

[lsu] Use dmem release address for release search
riscv-boom · Mar 30, 2020 · 644da07 · 644da07
2 parents a26504f + 9886dcf
commit 644da07
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala
@@ -995,7 +995,9 @@ class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
   // Load incoming and load retries go through both
 
   val lcam_addr  = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w),
-                                     RegNext(exe_tlb_paddr(w)), mem_paddr(w)))
+                                     RegNext(exe_tlb_paddr(w)),
+                                     Mux(fired_release(w), RegNext(io.dmem.release.bits.address),
+                                         mem_paddr(w))))
   val lcam_uop   = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop,
                                  Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp)))