Merge pull request #395 from riscv-boom/simplepoison

[core] Clean up how load-misses kill misspeculated load-wakeups
riscv-boom · Jan 4, 2020 · 690e82d · 690e82d
2 parents f5e0621 + cc1e8c2
commit 690e82d
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Showing 2 changed files with 7 additions and 12 deletions.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -677,9 +677,10 @@ class BoomCore(implicit p: Parameters) extends BoomModule
       // Fast Wakeup (uses just-issued uops that have known latencies)
       fast_wakeup.bits.uop := iss_uops(i)
       fast_wakeup.valid    := iss_valids(i) &&
-                                iss_uops(i).bypassable &&
-                                iss_uops(i).dst_rtype === RT_FIX &&
-                                iss_uops(i).ldst_val
+                              iss_uops(i).bypassable &&
+                              iss_uops(i).dst_rtype === RT_FIX &&
+                              iss_uops(i).ldst_val &&
+                              !(io.lsu.ld_miss && (iss_uops(i).iw_p1_poisoned || iss_uops(i).iw_p2_poisoned))
 
       // Slow Wakeup (uses write-port to register file)
       slow_wakeup.bits.uop := resp.bits.uop
@@ -717,11 +718,7 @@ class BoomCore(implicit p: Parameters) extends BoomModule
   }
 
   for ((renport, intport) <- rename_stage.io.wakeups zip int_ren_wakeups) {
-    // Stop wakeup for bypassable children of spec-loads trying to issue during a ldMiss.
-    renport.valid :=
-       intport.valid &&
-       !(io.lsu.ld_miss && (intport.bits.uop.iw_p1_poisoned || intport.bits.uop.iw_p2_poisoned))
-    renport.bits := intport.bits
+    renport <> intport
   }
   if (usingFPU) {
     for ((renport, fpport) <- fp_rename_stage.io.wakeups zip fp_pipeline.io.wakeups) {

diff --git a/src/main/scala/exu/issue-units/issue-slot.scala b/src/main/scala/exu/issue-units/issue-slot.scala
@@ -169,13 +169,11 @@ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
 
   for (i <- 0 until numWakeupPorts) {
     when (io.wakeup_ports(i).valid &&
-         (io.wakeup_ports(i).bits.pdst === next_uop.prs1) &&
-         !(io.ldspec_miss && io.wakeup_ports(i).bits.poisoned)) {
+         (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
       p1 := true.B
     }
     when (io.wakeup_ports(i).valid &&
-         (io.wakeup_ports(i).bits.pdst === next_uop.prs2) &&
-         !(io.ldspec_miss && io.wakeup_ports(i).bits.poisoned)) {
+         (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
       p2 := true.B
     }
     when (io.wakeup_ports(i).valid &&