Merge pull request #626 from riscv-boom/scala213

[WIP] Scala bump 2.13

build.sbt

@@ -1,4 +1,4 @@
 organization := "edu.berkeley.cs"
 version := "3.0"
 name := "boom"
-scalaVersion := "2.12.10"
+scalaVersion := "2.13.10"

src/main/scala/common/micro-op.scala

@@ -165,7 +165,7 @@ class CtrlSignals extends Bundle()
   val op1_sel     = UInt(OP1_X.getWidth.W)
   val op2_sel     = UInt(OP2_X.getWidth.W)
   val imm_sel     = UInt(IS_X.getWidth.W)
-  val op_fcn      = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W)
+  val op_fcn      = UInt((new freechips.rocketchip.rocket.ALUFN).SZ_ALU_FN.W)
   val fcn_dw      = Bool()
   val csr_cmd     = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
   val is_load     = Bool()   // will invoke TLB address lookup

src/main/scala/common/parameters.scala

@@ -96,6 +96,7 @@ case class BoomCoreParams(
   clockGate: Boolean = false,
   mcontextWidth: Int = 0,
   scontextWidth: Int = 0,
+  trace: Boolean = false,
 
   /* debug stuff */
   enableCommitLogPrintf: Boolean = false,
@@ -111,6 +112,11 @@ case class BoomCoreParams(
   val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop
   val retireWidth = decodeWidth
   val jumpInFrontend: Boolean = false // unused in boom
+  val useBitManip = false
+  val useBitManipCrypto = false
+  val useCryptoNIST = false
+  val useCryptoSM = false
+  val traceHasWdata = trace
 
   override def customCSRs(implicit p: Parameters) = new BoomCustomCSRs
 }
@@ -177,6 +183,7 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
   val usingFDivSqrt = boomParams.fpu.isDefined && boomParams.fpu.get.divSqrt
 
   val mulDivParams = boomParams.mulDiv.getOrElse(MulDivParams())
+  val trace = boomParams.trace
   // TODO: Allow RV32IF
   require(!(xLen == 32 && usingFPU), "RV32 does not support fp")
 

src/main/scala/common/tile.scala

@@ -22,8 +22,6 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 
-import testchipip.{ExtendedTracedInstruction, WithExtendedTraceport}
-
 import boom.exu._
 import boom.ifu._
 import boom.lsu._
@@ -49,7 +47,6 @@ case class BoomTileParams(
   icache: Option[ICacheParams] = Some(ICacheParams()),
   dcache: Option[DCacheParams] = Some(DCacheParams()),
   btb: Option[BTBParams] = Some(BTBParams()),
-  trace: Boolean = false,
   name: Option[String] = Some("boom_tile"),
   hartId: Int = 0
 ) extends InstantiableTileParams[BoomTile]
@@ -77,7 +74,6 @@ class BoomTile private(
   extends BaseTile(boomParams, crossing, lookup, q)
   with SinksExternalInterrupts
   with SourcesExternalNotifications
-  with WithExtendedTraceport
 {
 
   // Private constructor ensures altered LazyModule.p is used implicitly
@@ -156,7 +152,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
 
   Annotated.params(this, outer.boomParams)
 
-  val core = Module(new BoomCore(outer.boomParams.trace)(outer.p))
+  val core = Module(new BoomCore()(outer.p))
   val lsu  = Module(new LSU()(outer.p, outer.dcache.module.edge))
 
   val ptwPorts         = ListBuffer(lsu.io.ptw, outer.frontend.module.io.ptw, core.io.ptw_tlb)
@@ -168,8 +164,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
   outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
 
   // Pass through various external constants and reports
-  outer.extTraceSourceNode.bundle <> core.io.trace
-  outer.traceSourceNode.bundle <> DontCare
+  outer.traceSourceNode.bundle <> core.io.trace
   outer.bpwatchSourceNode.bundle <> DontCare // core.io.bpwatch
   core.io.hartid := outer.hartIdSinkNode.bundle
 
@@ -183,7 +178,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
   // PTW
   val ptw  = Module(new PTW(ptwPorts.length)(outer.dcache.node.edges.out(0), outer.p))
   core.io.ptw <> ptw.io.dpath
-  ptw.io.requestor <> ptwPorts
+  ptw.io.requestor <> ptwPorts.toSeq
   hellaCachePorts += ptw.io.mem
 
   // RoCC
@@ -235,7 +230,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
 
    // LSU IO
   val hellaCacheArb = Module(new HellaCacheArbiter(hellaCachePorts.length)(outer.p))
-  hellaCacheArb.io.requestor <> hellaCachePorts
+  hellaCacheArb.io.requestor <> hellaCachePorts.toSeq
   lsu.io.hellacache <> hellaCacheArb.io.mem
   outer.dcache.module.io.lsu <> lsu.io.dmem
 

src/main/scala/exu/core.scala

@@ -35,12 +35,10 @@ import chisel3.util._
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.Instructions._
-import freechips.rocketchip.rocket.{Causes, PRV}
+import freechips.rocketchip.rocket.{Causes, PRV, TracedInstruction}
 import freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle}
 import freechips.rocketchip.devices.tilelink.{PLICConsts, CLINTConsts}
 
-import testchipip.{ExtendedTracedInstruction}
-
 import boom.common._
 import boom.ifu.{GlobalHistory, HasBoomFrontendParameters}
 import boom.exu.FUConstants._
@@ -49,7 +47,7 @@ import boom.util._
 /**
  * Top level core object that connects the Frontend to the rest of the pipeline.
  */
-class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
+class BoomCore()(implicit p: Parameters) extends BoomModule
   with HasBoomFrontendParameters // TODO: Don't add this trait
 {
   val io = new freechips.rocketchip.tile.CoreBundle
@@ -61,7 +59,7 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
     val rocc = Flipped(new freechips.rocketchip.tile.RoCCCoreIO())
     val lsu = Flipped(new boom.lsu.LSUCoreIO)
     val ptw_tlb = new freechips.rocketchip.rocket.TLBPTWIO()
-    val trace = Output(Vec(coreParams.retireWidth, new ExtendedTracedInstruction))
+    val trace = Output(Vec(coreParams.retireWidth, new TracedInstruction))
     val fcsr_rm = UInt(freechips.rocketchip.tile.FPConstants.RM_SZ.W)
   }
   //**********************************
@@ -131,9 +129,9 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
                                                                    (if (usingRoCC) 1 else 0)))
   val iregister_read   = Module(new RegisterRead(
                            issue_units.map(_.issueWidth).sum,
-                           exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits),
+                           exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits).toSeq,
                            numIrfReadPorts,
-                           exe_units.withFilter(_.readsIrf).map(x => 2),
+                           exe_units.withFilter(_.readsIrf).map(x => 2).toSeq,
                            exe_units.numTotalBypassPorts,
                            jmp_unit.numBypassStages,
                            xLen))
@@ -1186,7 +1184,7 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
     // Connect FPIU
     ll_wbarb.io.in(1)        <> fp_pipeline.io.to_int
     // Connect FLDs
-    fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp)
+    fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp).toSeq
   }
   if (usingRoCC) {
     require(usingFPU)
@@ -1428,7 +1426,7 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
     }
   }
 
-  if (usingTrace) {
+  if (trace) {
     for (w <- 0 until coreWidth) {
       // Delay the trace so we have a cycle to pull PCs out of the FTQ
       io.trace(w).valid      := RegNext(rob.io.commit.arch_valids(w))

src/main/scala/exu/execution-units/execution-unit.scala

@@ -399,11 +399,11 @@ class ALUExeUnit(
   if (writesIrf) {
     io.iresp.valid     := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)
     io.iresp.bits.uop  := PriorityMux(iresp_fu_units.map(f =>
-      (f.io.resp.valid, f.io.resp.bits.uop)))
+      (f.io.resp.valid, f.io.resp.bits.uop)).toSeq)
     io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>
-      (f.io.resp.valid, f.io.resp.bits.data)))
+      (f.io.resp.valid, f.io.resp.bits.data)).toSeq)
     io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>
-      (f.io.resp.valid, f.io.resp.bits.predicated)))
+      (f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)
 
     // pulled out for critical path reasons
     // TODO: Does this make sense as part of the iresp bundle?
@@ -516,8 +516,8 @@ class FPUExeUnit(
   io.fresp.valid       := fu_units.map(_.io.resp.valid).reduce(_|_) &&
                           !(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))
   io.fresp.bits.uop    := PriorityMux(fu_units.map(f => (f.io.resp.valid,
-                                                         f.io.resp.bits.uop)))
-  io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)))
+                                                         f.io.resp.bits.uop)).toSeq)
+  io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)
   io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)
 
   // Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------

src/main/scala/exu/execution-units/functional-unit.scala

@@ -20,7 +20,6 @@ import chisel3._
 import chisel3.util._
 
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.rocket.ALU._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile
 import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}

src/main/scala/exu/fp-pipeline.scala

@@ -72,9 +72,9 @@ class FpPipeline(implicit p: Parameters) extends BoomModule with tile.HasFPUPara
                          ))
   val fregister_read = Module(new RegisterRead(
                          issue_unit.issueWidth,
-                         exe_units.withFilter(_.readsFrf).map(_.supportedFuncUnits),
+                         exe_units.withFilter(_.readsFrf).map(_.supportedFuncUnits).toSeq,
                          exe_units.numFrfReadPorts,
-                         exe_units.withFilter(_.readsFrf).map(x => 3),
+                         exe_units.withFilter(_.readsFrf).map(x => 3).toSeq,
                          0, // No bypass for FP
                          0,
                          fLen+1))