Merge pull request #341 from riscv-boom/ras-qor

[fcu/ras] RAS Update Regression
riscv-boom · Jul 25, 2019 · 7796d9f · 7796d9f
2 parents 1cec3fc + e67929c
commit 7796d9f
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/main/scala/ifu/fetch-control-unit.scala b/src/main/scala/ifu/fetch-control-unit.scala
@@ -443,7 +443,9 @@ class FetchControlUnit(implicit p: Parameters) extends BoomModule
   f3_req.valid := f3_valid && (bchecker.io.req.valid ||
                   (f3_bpd_may_redirect && !jal_overrides_bpd)) // && !(f0_redirect_val)
   f3_req.bits.addr := Mux(f3_bpd_overrides_bcheck, f3_bpd_redirect_target, bchecker.io.req.bits.addr)
-  io.f3_will_redirect := f3_req.valid
+
+  // This has a bad effect on QoR.
+  io.f3_will_redirect := false.B //f3_req.valid
 
   // TODO this logic is broken and vestigial. Do update correctly (remove RegNext)
   val f3_btb_update_bits = Wire(new BoomBTBUpdate)