Merge pull request #437 from riscv-boom/illegal_insn_suppress

[exu] Suppress illegal instructions from dispatching into the LSU or the RoCC queue
riscv-boom · Feb 6, 2020 · 779c62c · 779c62c
2 parents 1d4d0cd + 9ae154d
commit 779c62c
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -1422,7 +1422,9 @@ class BoomCore(implicit p: Parameters) extends BoomModule
     for (w <- 0 until coreWidth) {
        exe_units.rocc_unit.io.rocc.dis_rocc_vals(w) := (
          dis_fire(w) &&
-         dis_uops(w).uopc === uopROCC)
+         dis_uops(w).uopc === uopROCC &&
+         !dis_uops(w).exception
+       )
     }
   }
 

diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala
@@ -282,8 +282,8 @@ class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
     io.core.stq_full(w)    := stq_full
     io.core.dis_stq_idx(w) := st_enq_idx
 
-    val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq
-    val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq
+    val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception
+    val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception
     when (dis_ld_val)
     {
       ldq(ld_enq_idx).valid                := true.B