Merge pull request #376 from riscv-boom/rt_pas_fix

[ren] Fix RT_PAS passthrough
riscv-boom · Aug 25, 2019 · 781b68a · 781b68a
2 parents 60d0cb9 + 75a8568
commit 781b68a
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -511,7 +511,9 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
       val i_uop = rename_stage.io.ren2_uops(w)
       val f_uop = fp_rename_stage.io.ren2_uops(w)
 
-      dis_uops(w).prs1 := Mux(dis_uops(w).lrs1_rtype === RT_FLT, f_uop.prs1, i_uop.prs1)
+      // lrs1 can "pass through" to prs1. Used solely to index the csr file.
+      dis_uops(w).prs1 := Mux(dis_uops(w).lrs1_rtype === RT_FLT, f_uop.prs1,
+                          Mux(dis_uops(w).lrs1_rtype === RT_FIX, i_uop.prs1, dis_uops(w).lrs1))
       dis_uops(w).prs2 := Mux(dis_uops(w).lrs2_rtype === RT_FLT, f_uop.prs2, i_uop.prs2)
       dis_uops(w).prs3 := f_uop.prs3
       dis_uops(w).pdst := Mux(dis_uops(w).dst_rtype  === RT_FLT, f_uop.pdst, i_uop.pdst)

diff --git a/src/main/scala/exu/rename/rename-stage.scala b/src/main/scala/exu/rename/rename-stage.scala
@@ -223,8 +223,7 @@ class RenameStage(
   for ((uop, w) <- ren1_uops.zipWithIndex) {
     val mappings = maptable.io.map_resps(w)
 
-    // lrs1 can "pass through" to prs1. Used solely to index the csr file.
-    uop.prs1       := Mux(!float.B && uop.lrs1_rtype === RT_PAS, uop.lrs1, mappings.prs1)
+    uop.prs1       := mappings.prs1
     uop.prs2       := mappings.prs2
     uop.prs3       := mappings.prs3 // only FP has 3rd operand
     uop.stale_pdst := mappings.stale_pdst