Merge pull request #141 from riscv-boom/rvc

RVC Support

.circleci/config.yml

@@ -23,7 +23,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - run: 
                 name: Building riscv-tools
@@ -32,7 +32,7 @@ jobs:
                 no_output_timeout: 120m
 
             - save_cache:
-                key: riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                key: riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
                 paths:
                     - "/home/riscvuser/riscv-tools-install"
 
@@ -86,7 +86,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -121,7 +121,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -156,7 +156,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -191,7 +191,7 @@ jobs:
 #
 #           - restore_cache:
 #               keys:
-#                   - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+#                   - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 #
 #           - restore_cache:
 #               keys:
@@ -225,7 +225,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - run:
                 name: Run Scala checkstyle
@@ -249,7 +249,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -277,7 +277,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -306,7 +306,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -334,7 +334,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -363,7 +363,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -391,7 +391,7 @@ jobs:
 
             - restore_cache:
                 keys:
-                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 
             - restore_cache:
                 keys:
@@ -420,7 +420,7 @@ jobs:
 #
 #            - restore_cache:
 #                keys:
-#                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+#                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 #
 #            - restore_cache:
 #                keys:
@@ -448,7 +448,7 @@ jobs:
 #
 #            - restore_cache:
 #                keys:
-#                    - riscv-tools-installed-v2-{{ checksum "../rocket-chip.hash" }}
+#                    - riscv-tools-installed-v3-{{ checksum "../rocket-chip.hash" }}
 #
 #            - restore_cache:
 #                keys:
@@ -478,9 +478,10 @@ workflows:
                     - install-riscv-tools
 
             # Prepare the verilator builds
-            - prepare-boomconfig:
-                requires:
-                    - prepare-build-environment
+            # - prepare-boomconfig:
+            #     requires:
+            #         - prepare-riscv-tools
+
             - prepare-smallboomconfig:
                 requires:
                     - prepare-build-environment
@@ -492,13 +493,13 @@ workflows:
 #                    - prepare-build-environment
 
             # Run the respective tests
-            # Run the BoomConfig tests
-            - boomconfig-run-benchmark-tests:
-                requires:
-                    - prepare-boomconfig
-            - boomconfig-run-assembly-tests:
-                requires:
-                    - prepare-boomconfig
+            # Run the BoomConfig tests (Disabled due to memory limit)
+            # - boomconfig-run-benchmark-tests:
+            #     requires:
+            #         - prepare-boomconfig
+            # - boomconfig-run-assembly-tests:
+            #     requires:
+            #         - prepare-boomconfig
 
             # Run the SmallBoomConfig tests
             - smallboomconfig-run-benchmark-tests:

README.md

@@ -9,7 +9,7 @@ performance, synthesizable, and parameterizable core for architecture research.
 
 Feature | BOOM
 --- | ---
-ISA | RISC-V (RV64G)
+ISA | RISC-V (RV64GC)
 Synthesizable |√
 FPGA |√
 Parameterized |√
@@ -90,39 +90,12 @@ will also need to add $RISCV/bin to your $PATH.
 ````
    $ git clone https://github.com/riscv-boom/boom-template.git
    $ cd boom-template
-   $ ./scripts/build-tools.sh 
-````
-
-That's it. But read on for some more information about what's going on behind the scenes.
-
-By default, `riscv-tools/build.sh` builds a RV64GC compiler. Therefore, We need to change that as
-BOOM does not support the RVC extension.
-
-````
-   $ export RISCV=/path/to/install/riscv/toolchain
-   $ export PATH="${PATH}:$RISCV/bin"
-   $ git clone https://github.com/riscv-boom/boom-template.git
-   $ cd boom-template/rocket-chip
-   $ git submodule update --init
-   $ cd riscv-tools
    $ git submodule update --init --recursive
-   $ cp build.sh build-rv64g.sh
-   $ vim build-rv64g.sh
-````
-
-Modify the `riscv-gnu-toolchain` and `riscv-isa-sim` entries to specify rv64imafd as the ISA we want
-to build:
+   $ ./scripts/build-tools.sh
 
-````
-build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV --with-isa=rv64imafd
-build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=rv64imafd
 ````
 
-Now we can build the riscv-tools within (boom-template/rocket-chip/riscv-tools):
-
-````
-   $ ./build-rv64g.sh
-````
+That's it.
 
 For more detailed information on the toolchain, visit 
 [the riscv-tools repository](https://github.com/riscv/riscv-tools).
@@ -186,7 +159,7 @@ First verify the software is not an issue. Run spike first:
 
 ````
 # Verify it works on spike.
-spike --isa=rv64imafd my_program
+spike my_program
 
 # Then we can run on BOOM.
 ./emulator-freechips.rocketchip.system-SmallBoomConfig my_program 

ci/README.md

@@ -8,5 +8,5 @@ Things to look into:
 - How to build and test MegaBoomConfig (seems to error out saying "Killed/Error 137" which indicates OOM 
 since there is only 2GB of RAM per docker instance). So far as I can tell, the only way to fix this is to
 get a paid account with better docker instances (or to use machine for now and stop using once machine is a
-paid service which might happen soon).
+paid service which might happen soon). (Note 1/5/19 BoomConfig seems to suffer from same issue)
 

ci/build-riscv-tools.sh

@@ -10,54 +10,6 @@ if [ ! -d "$HOME/riscv-tools-install" ]; then
 
     cd $HOME/boom-template
 
-    echo "Initialize top-level submodules"
-    git submodule update --init
-
-    echo "Checking out rocket-chip with hash: $(cat boom/ROCKETCHIP_VERSION)"
-    cd rocket-chip
-    git fetch
-    git checkout $(cat ../boom/ROCKETCHIP_VERSION)
-
-    echo "Initializing riscv-tools"
-    git submodule update --init riscv-tools
-    cd riscv-tools
-    git submodule update --init --recursive riscv-isa-sim riscv-fesvr riscv-pk riscv-opcodes riscv-tests riscv-gnu-toolchain riscv-openocd
-
-    # We need to build a RV64G toolchain (not RVC which is the current riscv-tools default).
-    # Therefore, let's make our own build script and then invoke it.
-    f=build-rv64g.sh
-
-    echo "Build RV tools"
-    if [[ ! -e "$f" ]]
-    then
-        # If file doesn't exist, generate a new build script file.
-        echo "Generating script: rocket-chip/riscv-tools/$f"
-        echo "#! /bin/bash" >> $f
-        echo "#" >> $f
-        echo "# Script to build RISC-V ISA simulator, proxy kernel, and GNU toolchain." >> $f
-        echo "# Tools will be installed to \$RISCV." >> $f
-        echo "" >> $f
-        echo ". build.common" >> $f
-        echo "" >> $f
-        echo "echo "Starting RISC-V Toolchain build process"" >> $f
-        echo "echo "Tools will be installed to \$RISCV."" >> $f
-        echo "" >> $f
-        echo "build_project riscv-fesvr --prefix=\$RISCV" >> $f
-        echo "build_project riscv-isa-sim --prefix=\$RISCV --with-fesvr=\$RISCV --with-isa=rv64imafd" >> $f
-        echo "build_project riscv-gnu-toolchain --prefix=\$RISCV --with-arch=rv64imafd" >> $f
-        echo "CC= CXX= build_project riscv-pk --prefix=\$RISCV --host=riscv64-unknown-elf" >> $f
-        echo "build_project riscv-openocd --prefix=\$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror" >> $f
-        echo "build_project riscv-tests --prefix=\$RISCV/riscv64-unknown-elf" >> $f
-        echo "" >> $f
-        echo "echo \"RISC-V Toolchain installation completed!\"" >> $f
-    else
-        echo "Using existing $f script."
-    fi
-
-    chmod a+x $f && echo "./$f" && ./$f
-    retVal=$?
-    if [ ! $retVal -eq 0 ]; then
-        echo "A error has been encountered while building the toolchain."
-    fi
-    exit $retVal
+    # build the tools
+    ./scripts/build-tools.sh
 fi

docs/sections/FutureWork/futurework.rst

@@ -129,91 +129,3 @@ register file. While a 128-register scalar register file comes in at
 instruction-level parallelism (a three-issue BOOM with one FMA unit is 7
 read ports and 3 write ports).
 
-The Compressed (“C") ISA Extension
-----------------------------------
-
-.. _rvc:
-.. figure:: /figures/frontend.png
-    :alt: Frontend Pipeline 
-
-    The Fetch Unit. The grey box encompasses the Rocket front-end, which is re-used by BOOM.
-
-This section describes how to approach adding the Compressed ISA
-Extension to BOOM. The Compressed ISA Extension, or RVC
-(http://riscv.org/download.html#spec_compressed_isa) enables smaller, 16
-bit encodings of common instructions to decrease the static and dynamic
-code size. “RVC" comes with a number of features that are of particular
-interest to micro-architects:
-
--  All 16b instructions map directly into a longer 32b instruction.
-
--  32b instructions have no alignment requirement, and may start on a
-   half-word boundary.
-
-BOOM re-uses the front-end design from Rocket, a 5-stage in-order core.
-BOOM then takes instructions returning (the *fetch packet*) from the
-Rocket front-end, quickly decodes the instructions for branch
-prediction, and pushes the *fetch packet* into the *Fetch Buffer*.
-
-The C Extension provides the following challenges to micro-architects, a
-few include:
-
--  Increased decoding complexity (e.g., operands can now move around).
-
--  Finding *where* the instruction begins.
-
--  Tracking down :math:`+4` assumptions throughout the code base,
-   particularly with branch handling.
-
--  Unaligned instructions, in particular, running off cache lines and
-   virtual pages.
-
-The last point requires some additional “statefulness" in the Fetch
-Unit, as fetching all of the pieces of an instruction may take multiple
-cycles.
-
-The following describes the proposed implementation strategy of RVC in
-BOOM:
-
--  Implement RVC in the Rocket in-order core. Done properly, BOOM may
-   then gain RVC support almost entirely for free (modulo any :math:`+4`
-   assumptions in the code base).
-
--  Move BOOM’s *Fetch Buffer* into Rocket’s front-end. Rocket will need
-   the statefulness to handle wrap-around issues with fetching unaligned
-   32 bit instructions. A non-RVC Rocket core can optionally remove this
-   buffer.
-
--  Expand 16-bit instructions as they enter (or possibly exit) the
-   *Fetch Buffer*.
-
--  Minimize latency by placing 16b\ :math:`\rightarrow`\ 32b expanders
-   at every half-word start.
-
-Challenging Implementation Details
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-There are many challenging corner cases to consider with adding RVC
-support to BOOM. First, although all 16 bit encodings map to a 32b
-version, **the behavior of some 16b instructions are different from
-their 32b counterparts**! A JAL instruction writes the address of the
-following instruction to rd - but whether that is :math:`PC+2` or
-:math:`PC+4` depends on whether it’s the 16b JAL or a 32b JAL! Likewise,
-a mispredicted not-taken branch redirects the fetch unit to :math:`PC+2`
-or :math:`PC+4` depending on whether the branch was the compressed
-version or not. **Thus, the pipeline must track whether any given
-instruction was originally a compressed 16b instruction or not.**
-
-The branch prediction units will also require a careful rethink. The BTB
-tracks which instructions are *predicted-taken* branches and redirects
-the PC as desired. For a superscalar *fetch packet*, the BTB must help
-denote which instruction is to be blamed for the taken prediction to
-help mask off any invalid instructions that come afterward within the
-*fetch packet*. RVC makes this much more difficult, as some
-*predicted-taken* branches can wrap around fetch groupings/cache
-lines/virtual page boundaries. Thus, the “taken" prediction must be
-attached to a tag-hit on the *end* of the branch instruction. This
-handles fetching the first part of the branch (and predicting
-“not-taken"), then fetching the second part (which hits in the BTB and
-predicts “taken"), and only then redirecting the front-end to the
-predicted-taken PC target.