Stage/Phase Rocket Chip Bump (#453)

* Intermediate RC Bump * Remove clock and reset from TracedInstruction * Blanket DontCare coreMonitorBundle * Remove unused diplomatic object model stuff * Remove an unused comment * Remove unused rocket params
riscv-boom · Apr 18, 2020 · 90911dd · 90911dd
1 parent 10eeee4
commit 90911dd
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Showing 2 changed files with 2 additions and 49 deletions.
diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
@@ -14,7 +14,7 @@ import freechips.rocketchip.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalModuleTree, LogicalTreeNode, RocketLogicalTreeNode, ICacheLogicalTreeNode}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode }
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.subsystem.{RocketCrossingParams}
 import freechips.rocketchip.tilelink._
@@ -145,36 +145,6 @@ class BoomTile(
     else TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none)
   }
 
-  val fakeRocketParams = RocketTileParams(
-    dcache = boomParams.dcache,
-    hartId = boomParams.hartId,
-    name   = boomParams.name,
-    btb    = boomParams.btb,
-    core = RocketCoreParams(
-      bootFreqHz          = boomParams.core.bootFreqHz,
-      useVM               = boomParams.core.useVM,
-      useUser             = boomParams.core.useUser,
-      useDebug            = boomParams.core.useDebug,
-      useAtomics          = boomParams.core.useAtomics,
-      useAtomicsOnlyForIO = boomParams.core.useAtomicsOnlyForIO,
-      useCompressed       = boomParams.core.useCompressed,
-      useSCIE             = boomParams.core.useSCIE,
-      mulDiv              = boomParams.core.mulDiv,
-      fpu                 = boomParams.core.fpu,
-      nLocalInterrupts    = boomParams.core.nLocalInterrupts,
-      nPMPs               = boomParams.core.nPMPs,
-      nBreakpoints        = boomParams.core.nBreakpoints,
-      nPerfCounters       = boomParams.core.nPerfCounters,
-      haveBasicCounters   = boomParams.core.haveBasicCounters,
-      misaWritable        = boomParams.core.misaWritable,
-      haveCFlush          = boomParams.core.haveCFlush,
-      nL2TLBEntries       = boomParams.core.nL2TLBEntries,
-      mtvecInit           = boomParams.core.mtvecInit,
-      mtvecWritable       = boomParams.core.mtvecWritable
-    )
-  )
-  val rocketLogicalTree: RocketLogicalTreeNode = new RocketLogicalTreeNode(cpuDevice, fakeRocketParams, dtim_adapter, p(XLen))
-
   override lazy val module = new BoomTileModuleImp(this)
 
   // DCache
@@ -187,9 +157,6 @@ class BoomTile(
   val frontend = LazyModule(new BoomFrontend(tileParams.icache.get, hartId))
   tlMasterXbar.node := frontend.masterNode
 
-  private val deviceOpt = None
-  val iCacheLogicalTreeNode = new BoomICacheLogicalTreeNode(frontend.icache, deviceOpt, tileParams.icache.get)
-
   // ROCC
   val roccs = p(BuildRoCC).map(_(p))
   roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl }

diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -1344,20 +1344,9 @@ class BoomCore(implicit p: Parameters) extends BoomModule
 
   // TODO: Does anyone want this debugging functionality?
   val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen))
+  coreMonitorBundle := DontCare
   coreMonitorBundle.clock  := clock
   coreMonitorBundle.reset  := reset
-  coreMonitorBundle.hartid := DontCare
-  coreMonitorBundle.timer  := DontCare
-  coreMonitorBundle.valid  := DontCare
-  coreMonitorBundle.pc     := DontCare
-  coreMonitorBundle.wrdst  := DontCare
-  coreMonitorBundle.wrdata := DontCare
-  coreMonitorBundle.wren   := DontCare
-  coreMonitorBundle.rd0src := DontCare
-  coreMonitorBundle.rd0val := DontCare
-  coreMonitorBundle.rd1src := DontCare
-  coreMonitorBundle.rd1val := DontCare
-  coreMonitorBundle.inst   := DontCare
 
   //-------------------------------------------------------------
   //-------------------------------------------------------------
@@ -1430,9 +1419,6 @@ class BoomCore(implicit p: Parameters) extends BoomModule
 
   if (p(BoomTilesKey)(0).trace) {
     for (w <- 0 until coreWidth) {
-      io.trace(w).clock      := clock
-      io.trace(w).reset      := reset
-
       // Delay the trace so we have a cycle to pull PCs out of the FTQ
       io.trace(w).valid      := RegNext(rob.io.commit.valids(w))