Merge pull request #384 from riscv-boom/flatten

[tile] Flatten BOOM Tile organization

src/main/scala/common/tile.scala

@@ -6,12 +6,15 @@
 package boom.common
 
 import chisel3._
+import chisel3.util.{RRArbiter, Queue}
+
+import scala.collection.mutable.ListBuffer
 
 import freechips.rocketchip.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalModuleTree, LogicalTreeNode, RocketLogicalTreeNode}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalModuleTree, LogicalTreeNode, RocketLogicalTreeNode, ICacheLogicalTreeNode}
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.subsystem.RocketCrossingParams
 import freechips.rocketchip.tilelink._
@@ -72,10 +75,6 @@ class BoomTile(
   extends BaseTile(boomParams, crossing, lookup, q)
   with SinksExternalInterrupts
   with SourcesExternalNotifications
-  with HasBoomLazyRoCC  // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
-  with CanHaveBoomPTW
-  with HasBoomICacheFrontend
-  with HasBoomLSU
 {
 
   // Private constructor ensures altered LazyModule.p is used implicitly
@@ -137,8 +136,6 @@ class BoomTile(
     Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
   }
 
-  override lazy val module = new BoomTileModuleImp(this)
-
   override def makeMasterBoundaryBuffers(implicit p: Parameters) = {
     if (!boomParams.boundaryBuffers) super.makeMasterBoundaryBuffers
     else TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1))
@@ -179,38 +176,48 @@ class BoomTile(
   )
   val rocketLogicalTree: RocketLogicalTreeNode = new RocketLogicalTreeNode(cpuDevice, fakeRocketParams, dtim_adapter, p(XLen))
 
+
+  override lazy val module = new BoomTileModuleImp(this)
+
+  // DCache
+  lazy val dcache: BoomNonBlockingDCache = LazyModule(new BoomNonBlockingDCache(hartId))
+  val dCacheTap = TLIdentityNode()
+  tlMasterXbar.node := dCacheTap := dcache.node
+
+
+  // Frontend/ICache
+  val frontend = LazyModule(new BoomFrontend(tileParams.icache.get, hartId))
+  tlMasterXbar.node := frontend.masterNode
+
+  private val deviceOpt = None
+  val iCacheLogicalTreeNode = new ICacheLogicalTreeNode(deviceOpt, tileParams.icache.get)
+
+
+  // ROCC
+  val roccs = p(BuildRoCC).map(_(p))
+  roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl }
+  roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl }
+
 }
 
 /**
- * BOOM tile implicit
+ * BOOM tile implementation
  *
  * @param outer top level BOOM tile
  */
-class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer)
-  with HasBoomLazyRoCCModule
-  with CanHaveBoomPTWModule
-  with HasBoomICacheFrontendModule
-  with HasBoomLSUModule
-{
+class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
+
   Annotated.params(this, outer.boomParams)
 
   val core = Module(new BoomCore()(outer.p))
+  val lsu  = Module(new LSU()(outer.p, outer.dcache.module.edge))
 
-  // Observe the Tilelink Channel C traffic leaving the L1D (writeback/releases).
-  val tl_c = outer.dCacheTap.out(0)._1.c
-  core.io.release.valid := tl_c.fire()
-  core.io.release.bits.address := tl_c.bits.address
 
-  // Report unrecoverable error conditions; for now the only cause is cache ECC errors
-  // outer.reportHalt(List(outer.frontend.module.io.errors, outer.dcache.module.io.errors))
-  // ECC is not supported
+  var nPTWPorts        = 3
+  val ptwPorts         = ListBuffer(lsu.io.ptw, outer.frontend.module.io.ptw, core.io.ptw_tlb)
 
-  // Report when the tile has ceased to retire instructions; for now the only cause is clock gating
-  //outer.reportCease(outer.boomParams.core.clockGate.option(
-  //  !outer.dcache.module.io.cpu.clock_enabled &&
-  //  !outer.frontend.module.io.cpu.clock_enabled &&
-  //  !ptw.io.dpath.clock_enabled &&
-  //  core.io.cease)) // clock-gating is not supported
+  var nHellaCachePorts = 0
+  val hellaCachePorts  = ListBuffer[HellaCacheIO]()
 
   outer.reportWFI(None) // TODO: actually report this?
 
@@ -235,30 +242,75 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer)
   core.io.lsu <> lsu.io.core
 
   //fpuOpt foreach { fpu => core.io.fpu <> fpu.io } RocketFpu - not needed in boom
-  core.io.ptw <> ptw.io.dpath
-  fcsr_rm := core.io.fcsr_rm
   core.io.rocc := DontCare
   core.io.reset_vector := DontCare
 
 
   if (outer.roccs.size > 0) {
-    cmdRouter.get.io.in <> core.io.rocc.cmd
+    val (respArb, cmdRouter) = {
+      val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size))
+      val cmdRouter = Module(new RoccCommandRouter(outer.roccs.map(_.opcodes))(outer.p))
+      outer.roccs.zipWithIndex.foreach { case (rocc, i) =>
+        nPTWPorts += 1
+        ptwPorts ++= rocc.module.io.ptw
+        rocc.module.io.cmd <> cmdRouter.io.out(i)
+        val dcIF = Module(new SimpleHellaCacheIF()(outer.p))
+        dcIF.io.requestor <> rocc.module.io.mem
+        nHellaCachePorts += 1
+        hellaCachePorts += dcIF.io.cache
+        respArb.io.in(i) <> Queue(rocc.module.io.resp)
+      }
+      // Create this FPU just for RoCC
+      val nFPUPorts = outer.roccs.filter(_.usesFPU).size
+      if (nFPUPorts > 0) {
+        val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new freechips.rocketchip.tile.FPU(params)(outer.p)))
+        // TODO: Check this FPU works properly
+        fpuOpt foreach { fpu =>
+          // This FPU does not get CPU requests
+          fpu.io := DontCare
+          fpu.io.fcsr_rm := core.io.fcsr_rm
+          fpu.io.dmem_resp_val := false.B
+          fpu.io.valid := false.B
+          fpu.io.killx := false.B
+          fpu.io.killm := false.B
+
+          val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts))
+          val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io)
+          fpArb.io.in_req <> fp_rocc_ios.map(_.fpu_req)
+          fp_rocc_ios.zip(fpArb.io.in_resp).foreach {
+            case (rocc, arb) => rocc.fpu_resp <> arb
+          }
+          fpu.io.cp_req <> fpArb.io.out_req
+          fpArb.io.out_resp <> fpu.io.cp_resp
+        }
+      }
+      (respArb, cmdRouter)
+    }
+
+    cmdRouter.io.in <> core.io.rocc.cmd
     outer.roccs.foreach(_.module.io.exception := core.io.rocc.exception)
-    core.io.rocc.resp <> respArb.get.io.out
-    core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_||_))
+    core.io.rocc.resp <> respArb.io.out
+    core.io.rocc.busy <> (cmdRouter.io.busy || outer.roccs.map(_.module.io.busy).reduce(_||_))
     core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_||_)
   }
 
 
-  // TODO eliminate this redundancy
-  val h = hellaCachePorts.size
-  val o = outer.nHellaCachePorts
-  require(h == o, s"port list size was $h, outer counted $o")
-  // TODO figure out how to move the below into their respective mix-ins
-  hellaCacheArb.io.requestor <> hellaCachePorts
-  ptwPorts += core.io.ptw_tlb
+
+  // PTW
+  val ptw  = Module(new PTW(nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
+  core.io.ptw <> ptw.io.dpath
   ptw.io.requestor <> ptwPorts
+  nHellaCachePorts += 1
+  hellaCachePorts += ptw.io.mem
+
+   // LSU IO
+  val hellaCacheArb = Module(new HellaCacheArbiter(nHellaCachePorts)(outer.p))
+  hellaCacheArb.io.requestor <> hellaCachePorts
+  lsu.io.hellacache <> hellaCacheArb.io.mem
+  outer.dcache.module.io.lsu <> lsu.io.dmem
+
 
+  // Generate a descriptive string
   val frontendStr = outer.frontend.module.toString
   val coreStr = core.toString
   val boomTileStr =

src/main/scala/exu/core.scala

@@ -60,7 +60,6 @@ trait HasBoomCoreIO extends freechips.rocketchip.tile.HasTileParameters
     val ptw_tlb = new freechips.rocketchip.rocket.TLBPTWIO()
     val trace = Output(Vec(coreParams.retireWidth,
       new freechips.rocketchip.rocket.TracedInstruction))
-    val release = Flipped(Valid(new boom.lsu.ReleaseInfo))
     val fcsr_rm = UInt(freechips.rocketchip.tile.FPConstants.RM_SZ.W)
   }
 }

src/main/scala/ifu/frontend.scala

@@ -29,7 +29,6 @@ import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{ICacheLogicalTree
 import boom.bpu._
 import boom.common._
 import boom.exu.{BranchUnitResp, CommitExceptionSignals}
-import boom.lsu.{CanHaveBoomPTW, CanHaveBoomPTWModule}
 import boom.util.{BoomCoreStringPrefix}
 
 /**
@@ -334,31 +333,4 @@ class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
     + icache.toString)
 }
 
-/**
- * Mix-in for constructing tiles that have an ICache-based pipeline frontend
- */
-trait HasBoomICacheFrontend extends CanHaveBoomPTW
-{
-  this: BaseTile =>
-  val module: HasBoomICacheFrontendModule
-  val frontend = LazyModule(new BoomFrontend(tileParams.icache.get, hartId))
-  tlMasterXbar.node := frontend.masterNode
-  connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes)
-  nPTWPorts += 1
-  nPTWPorts += 1 // boom -- needs an extra PTW port for its LSU.
-
-  private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None
-
-  val iCacheLogicalTreeNode = new ICacheLogicalTreeNode(deviceOpt, tileParams.icache.get)
-
-}
-
-/**
- * Mix-in for constructing tiles that have an ICache-based pipeline frontend
- */
-trait HasBoomICacheFrontendModule extends CanHaveBoomPTWModule
-{
-  val outer: HasBoomICacheFrontend
-  ptwPorts += outer.frontend.module.io.ptw
-}