Move visibility node in front of the width adapteR

riscv-boom · Feb 12, 2023 · 9616e24 · 9616e24
1 parent 615f4ef
commit 9616e24
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
@@ -81,7 +81,7 @@ class BoomTile private(
     this(params, crossing.crossingType, lookup, p)
 
   val intOutwardNode = IntIdentityNode()
-  val masterNode = visibilityNode
+  val masterNode = TLIdentityNode()
   val slaveNode = TLIdentityNode()
 
   val tile_master_blocker =
@@ -129,14 +129,16 @@ class BoomTile private(
   // DCache
   lazy val dcache: BoomNonBlockingDCache = LazyModule(new BoomNonBlockingDCache(staticIdForMetadataUseOnly))
   val dCacheTap = TLIdentityNode()
-  tlMasterXbar.node := dCacheTap := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node
+  tlMasterXbar.node := dCacheTap := TLWidthWidget(tileParams.dcache.get.rowBits/8) := visibilityNode := dcache.node
 
 
   // Frontend/ICache
   val frontend = LazyModule(new BoomFrontend(tileParams.icache.get, staticIdForMetadataUseOnly))
   frontend.resetVectorSinkNode := resetVectorNexusNode
   tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode
 
+  require(tileParams.dcache.get.rowBits == tileParams.icache.get.rowBits)
+
   // ROCC
   val roccs = p(BuildRoCC).map(_(p))
   roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl }