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Decouple from SBus width (#623)
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@jerryz123
jerryz123 committed Nov 22, 2022
1 parent 6b7e26e commit 9e42690
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Showing 2 changed files with 14 additions and 21 deletions.
31 changes: 12 additions & 19 deletions src/main/scala/common/config-mixins.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -110,18 +110,17 @@ class WithNSmallBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
),
icache = Some(
ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, fetchBytes=2*4)
ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=2*4)
),
hartId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
case XLen => 64
})
)
Expand Down Expand Up @@ -157,18 +156,17 @@ class WithNMediumBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
),
icache = Some(
ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=4, fetchBytes=2*4)
ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=2*4)
),
hartId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
case XLen => 64
})
)
Expand Down Expand Up @@ -203,18 +201,17 @@ class WithNLargeBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=4, nTLBWays=16)
DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=4, nTLBWays=16)
),
icache = Some(
ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, fetchBytes=4*4)
ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4)
),
hartId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16)
case XLen => 64
})
)
Expand Down Expand Up @@ -251,18 +248,17 @@ class WithNMegaBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends C
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
),
icache = Some(
ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, fetchBytes=4*4)
ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4)
),
hartId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16)
case XLen => 64
})
)
Expand Down Expand Up @@ -299,18 +295,17 @@ class WithNGigaBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends C
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
),
icache = Some(
ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=8, fetchBytes=4*4)
ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4)
),
hartId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16)
case XLen => 64
})
)
Expand Down Expand Up @@ -351,7 +346,7 @@ class WithNCS152BaselineBooms(n: Int = 1, overrideIdOffset: Option[Int] = None)
// DO NOT CHANGE ABOVE
),
dcache = Some(DCacheParams(
rowBits=site(SystemBusKey).beatBytes*8,
rowBits=64,
nSets=64, // CS152: Change me (must be pow2, 2-64)
nWays=4, // CS152: Change me (1-8)
nMSHRs=2 // CS152: Change me (1+)
Expand All @@ -362,7 +357,6 @@ class WithNCS152BaselineBooms(n: Int = 1, overrideIdOffset: Option[Int] = None)
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
case XLen => 64
})
)
Expand Down Expand Up @@ -401,7 +395,7 @@ class WithNCS152DefaultBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) e
// DO NOT CHANGE ABOVE
),
dcache = Some(DCacheParams(
rowBits=site(SystemBusKey).beatBytes*8,
rowBits=64,
nSets=64, // CS152: Change me (must be pow2, 2-64)
nWays=4, // CS152: Change me (1-8)
nMSHRs=2 // CS152: Change me (1+)
Expand All @@ -412,7 +406,6 @@ class WithNCS152DefaultBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) e
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
case XLen => 64
})
)
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/common/tile.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,13 +133,13 @@ class BoomTile private(
// DCache
lazy val dcache: BoomNonBlockingDCache = LazyModule(new BoomNonBlockingDCache(staticIdForMetadataUseOnly))
val dCacheTap = TLIdentityNode()
tlMasterXbar.node := dCacheTap := dcache.node
tlMasterXbar.node := dCacheTap := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node


// Frontend/ICache
val frontend = LazyModule(new BoomFrontend(tileParams.icache.get, staticIdForMetadataUseOnly))
frontend.resetVectorSinkNode := resetVectorNexusNode
tlMasterXbar.node := frontend.masterNode
tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode

// ROCC
val roccs = p(BuildRoCC).map(_(p))
Expand Down

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