Connect local clock and reset to each element in trace port (#433)

riscv-boom · Jan 23, 2020 · a88fe70 · a88fe70
1 parent 7ba342a
commit a88fe70
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -1427,6 +1427,8 @@ class BoomCore(implicit p: Parameters) extends BoomModule
 
   if (p(BoomTilesKey)(0).trace) {
     for (w <- 0 until coreWidth) {
+      io.trace(w).clock      := clock
+      io.trace(w).reset      := reset
       io.trace(w).valid      := rob.io.commit.valids(w)
       io.trace(w).iaddr      := Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen)
       io.trace(w).insn       := rob.io.commit.uops(w).debug_inst