Fix trace interrupt/exception signals

riscv-boom · Feb 2, 2023 · a9c9448 · a9c9448
1 parent 98487c6
commit a9c9448
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -1465,8 +1465,8 @@ class BoomCore()(implicit p: Parameters) extends BoomModule
       // These csr signals do not exactly match up with the ROB commit signals.
       io.trace(w).priv       := RegNext(csr.io.status.prv)
       // Can determine if it is an interrupt or not based on the MSB of the cause
-      io.trace(w).exception  := RegNext(rob.io.com_xcpt.valid && !rob.io.com_xcpt.bits.cause(xLen - 1))
-      io.trace(w).interrupt  := RegNext(rob.io.com_xcpt.valid && rob.io.com_xcpt.bits.cause(xLen - 1))
+      io.trace(w).exception  := RegNext(rob.io.com_xcpt.valid && !rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B
+      io.trace(w).interrupt  := RegNext(rob.io.com_xcpt.valid && rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B
       io.trace(w).cause      := RegNext(rob.io.com_xcpt.bits.cause)
       io.trace(w).tval       := RegNext(csr.io.tval)
     }