[exu] Refactor fp stdatagen as output of FPIU unit

src/main/scala/exu/execution-units/execution-unit.scala

@@ -454,12 +454,13 @@ class FPUExeUnit(
       reads_frf  = true,
       writes_frf = true,
       writes_ll_irf = has_fpiu,
+      writes_irf = has_fpiu, // HACK: the "irf" port actually goes to the LSU fpu SDATAGen
       num_bypass_stages = 0,
       data_width = p(tile.TileKey).core.fpu.get.fLen + 1,
       bypassable = false,
       has_fpu  = has_fpu,
       has_fdiv = has_fdiv,
-      has_fpiu = has_fpiu)(p)
+      has_fpiu = has_fpiu)(p) with tile.HasFPUParameters
 {
    assert(!(has_fpu && !has_fpiu), "FPU units must contain FPIU")
    // TODO: Separate out FPIU so this isn't needed.
@@ -557,7 +558,9 @@ class FPUExeUnit(
       // buffer up results since we share write-port on integer regfile.
       val queue = Module(new BranchKillableQueue(new ExeUnitResp(data_width),
          entries = dfmaLatency + 3)) // TODO being overly conservative
-      queue.io.enq.valid       := fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I)
+      queue.io.enq.valid       := (fpu.io.resp.valid &&
+                                   fpu.io.resp.bits.uop.fu_code_is(FU_F2I) &&
+                                   fpu.io.resp.bits.uop.uopc =/= uopSTD)
       queue.io.enq.bits.uop    := fpu.io.resp.bits.uop
       queue.io.enq.bits.data   := fpu.io.resp.bits.data
       queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags
@@ -567,6 +570,10 @@ class FPUExeUnit(
 
       fpiu_busy := !(queue.io.empty)
 
+      io.iresp.valid     := io.req.valid && io.req.bits.uop.uopc === uopSTD
+      io.iresp.bits.uop  := io.req.bits.uop
+      io.iresp.bits.data := ieee(io.req.bits.rs2_data)
+
       assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue.
    }
 

src/main/scala/exu/execution-units/execution-units.scala

@@ -160,12 +160,11 @@ class ExecutionUnits(fpu: Boolean)(implicit val p: Parameters) extends HasBoomCo
    else
    {
       val fp_width = issueParams.find(_.iqType == IQT_FP.litValue).get.issueWidth
-      require (fp_width == 1) // TODO hacks to fix include uopSTD_fp needing a proper func unit.
       for (w <- 0 until fp_width)
       {
          val fpuExeUnit = Module(new FPUExeUnit(has_fpu = true,
-                                            has_fdiv = usingFDivSqrt && (w==0),
-                                            has_fpiu = (w==0)))
+                                                has_fdiv = usingFDivSqrt && (w==0),
+                                                has_fpiu = (w==0)))
          fpuExeUnit.io.status := DontCare
          fpuExeUnit.io.lsu_io := DontCare
          fpuExeUnit.io.dmem := DontCare

src/main/scala/exu/fp-pipeline.scala

@@ -113,7 +113,7 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
       {
          issue_unit.io.dis_valids(w) := io.dis_valids(w)
          issue_unit.io.dis_uops(w).uopc := uopSTD
-         issue_unit.io.dis_uops(w).fu_code := FUConstants.FU_FPU
+         issue_unit.io.dis_uops(w).fu_code := FUConstants.FU_F2I
          issue_unit.io.dis_uops(w).lrs1_rtype := RT_X
          issue_unit.io.dis_uops(w).prs1_busy := false.B
       }
@@ -173,20 +173,6 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
    {
       ex.io.req <> fregister_read.io.exe_reqs(w)
       require (!ex.bypassable)
-
-      // TODO HACK only let one FPU issue port issue these.
-      // Solution : Make STDataGen a functional unit time
-      require (w == 0)
-      when (fregister_read.io.exe_reqs(w).bits.uop.uopc === uopSTD)
-      {
-         ex.io.req.valid :=  false.B
-      }
-
-      io.tosdq.valid    := fregister_read.io.exe_reqs(w).bits.uop.uopc === uopSTD
-      io.tosdq.bits.uop := fregister_read.io.exe_reqs(w).bits.uop
-      val sdata = fregister_read.io.exe_reqs(w).bits.rs2_data
-
-      io.tosdq.bits.data := ieee(sdata)
    }
    require (exe_units.num_total_bypass_ports == 0)
 
@@ -222,7 +208,6 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
    when (ifpu_resp.valid) { assert (ifpu_resp.bits.uop.ctrl.rf_wen && ifpu_resp.bits.uop.dst_rtype === RT_FLT) }
 
    var w_cnt = 1
-   var toint_found = false
    for (eu <- exe_units)
    {
       if (eu.writes_frf)
@@ -245,6 +230,9 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
 
    val fpiu_unit = exe_units.fpiu_unit
    io.toint <> fpiu_unit.io.ll_iresp
+   io.tosdq.valid := fpiu_unit.io.iresp.valid
+   io.tosdq.bits  := fpiu_unit.io.iresp.bits
+   fpiu_unit.io.iresp.ready := true.B
 
    //-------------------------------------------------------------
    //-------------------------------------------------------------