fix Generator.scala to emit correct set of tests to be run by BOOM wi…

…th no fpu

disabling fpu should show the correct set of supported extensions in dts

src/main/scala/common/configs.scala

@@ -57,7 +57,7 @@ class DefaultBoomConfig extends Config((site, here, up) => {
 
 class WithoutBoomFPU extends Config((site, here, up) => {
    case BoomTilesKey => up(BoomTilesKey, site) map { r => r.copy(core = r.core.copy(
-      usingFPU = false))
+      fpu = None))
    }
 })
 

src/main/scala/common/parameters.scala

@@ -126,7 +126,6 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
    //************************************
    // Functional Units
    val usingFDivSqrt = boomParams.fpu.isDefined && boomParams.fpu.get.divSqrt
-   override val usingFPU      = boomParams.usingFPU
 
    val mulDivParams = boomParams.mulDiv.getOrElse(MulDivParams())
 

src/main/scala/exu/core.scala

@@ -68,7 +68,6 @@ trait HasBoomCoreIO extends freechips.rocketchip.tile.HasTileParameters {
 
 class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdgeOut) extends BoomModule()(p)
    with HasBoomCoreIO
-   with freechips.rocketchip.tile.HasFPUParameters
 {
    //**********************************
    // construct all of the modules
@@ -109,7 +108,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
                                  xLen,
                                  exe_units.bypassable_write_port_mask))
                           }
-   val ll_wbarb         = Module(new Arbiter(new ExeUnitResp(xLen), 2))
+   val ll_wbarb         = Module(new Arbiter(new ExeUnitResp(xLen), if (usingFPU) 2 else 1))
    val iregister_read   = Module(new RegisterRead(
                                  issue_units.map(_.issue_width).sum,
                                  exe_units.withFilter(_.usesIRF).map(_.supportedFuncUnits),
@@ -1073,12 +1072,12 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    }
 
    if (usingFPU) {
-      for (wakeup <- fp_pipeline.io.wakeups)
+      for ((wdata, wakeup) <- fp_pipeline.io.debug_wb_wdata zip fp_pipeline.io.wakeups)
       {
          rob.io.wb_resps(cnt) <> wakeup
          rob.io.fflags(f_cnt) <> wakeup.bits.fflags
          rob.io.debug_wb_valids(cnt) := wakeup.valid
-         rob.io.debug_wb_wdata(cnt) := ieee(wakeup.bits.data)
+         rob.io.debug_wb_wdata(cnt) := wdata
          cnt += 1
          f_cnt += 1
 

src/main/scala/exu/fppipeline.scala

@@ -51,6 +51,7 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
       val wb_pdsts         = Input(Vec(num_wakeup_ports, UInt(width=fp_preg_sz.W)))
 
       val debug_tsc_reg    = Input(UInt(width=xLen.W))
+      val debug_wb_wdata   = Output(Vec(num_wakeup_ports, UInt((fLen+1).W)))
    }
 
    //**********************************
@@ -299,6 +300,9 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
       }
    }
 
+   for ((wdata, wakeup) <- io.debug_wb_wdata zip io.wakeups) {
+      wdata := ieee(wakeup.bits.data)
+   }
 
    exe_units.map(_.io.fcsr_rm := io.fcsr_rm)
 

src/main/scala/exu/functional_unit.scala

@@ -585,7 +585,6 @@ class MemAddrCalcUnit(implicit p: Parameters)
       is_branch_unit = false)(p)
    with freechips.rocketchip.rocket.constants.MemoryOpConstants
    with freechips.rocketchip.rocket.constants.ScalarOpConstants
-   with freechips.rocketchip.tile.HasFPUParameters
 {
    // perform address calculation
    val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt

src/main/scala/exu/rename.scala

@@ -204,6 +204,7 @@ class RenameStage(
    {
       val imap = imaptable.io.values(w)
       val fmap = if (usingFPU) fmaptable.io.values(w) else Wire(new MapTableOutput(1))
+      if (!usingFPU) fmap := DontCare
 
       uop.pop1       := Mux(uop.lrs1_rtype === RT_FLT, fmap.prs1, imap.prs1)
       uop.pop2       := Mux(uop.lrs2_rtype === RT_FLT, fmap.prs2, imap.prs2)
@@ -303,6 +304,7 @@ class RenameStage(
    {
       val ibusy = ibusytable.io.values(w)
       val fbusy = if (usingFPU) fbusytable.io.values(w) else Wire(new BusyTableOutput)
+      if (!usingFPU) fbusy := DontCare
 
       uop.prs1_busy := Mux(uop.lrs1_rtype === RT_FLT, fbusy.prs1_busy, ibusy.prs1_busy)
       uop.prs2_busy := Mux(uop.lrs2_rtype === RT_FLT, fbusy.prs2_busy, ibusy.prs2_busy)

src/main/scala/system/Generator.scala

@@ -69,12 +69,10 @@ object Generator extends GeneratorApp {
         if (cfg.fLen >= 64) {
           TestGeneration.addSuites(env.map(rv32ud))
         }
-      } else {
-        TestGeneration.addSuite(rv32udBenchmarks)
-        TestGeneration.addSuites(env.map(rv64uf))
-        if (cfg.fLen >= 64) {
+      } else if (cfg.fLen >= 64) {
           TestGeneration.addSuites(env.map(rv64ud))
-        }
+          TestGeneration.addSuites(env.map(rv64uf))
+          TestGeneration.addSuite(rv32udBenchmarks)
       }
     }
     if (coreParams.useAtomics) {