Merge pull request #490 from riscv-boom/icache-flush-fix

[ifu] Fix spurious ICache flush by invalid instructions
riscv-boom · Aug 30, 2020 · c10da82 · c10da82
2 parents 3045048 + cf4d748
commit c10da82
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -378,7 +378,7 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
 
   io.ifu.flush_icache := (0 until coreWidth).map { i =>
     (rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) ||
-    (dec_uops(i).is_jalr && csr.io.status.debug)
+    (RegNext(dec_valids(i) && dec_uops(i).is_jalr && csr.io.status.debug))
   }.reduce(_||_)
 
   // TODO FIX THIS HACK