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Make BranchDecoder use existing ComputeTarget functions
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@jerryz123
jerryz123 committed Feb 22, 2019
1 parent c0801f3 commit c26e3d2
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Showing 5 changed files with 28 additions and 44 deletions.
31 changes: 9 additions & 22 deletions src/main/scala/common/consts.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ import chisel3.util._

import freechips.rocketchip.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander

/**
* Mixin indicating the debug flags that can be set for viewing different
Expand Down Expand Up @@ -346,42 +347,28 @@ trait RISCVConstants
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)

def IsCall(inst: UInt)(implicit p: Parameters): Bool =
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt =
{
val rvc_exp = Module(new freechips.rocketchip.rocket.RVCExpander)
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
val e_inst = Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)

(e_inst === freechips.rocketchip.rocket.Instructions.JAL ||
e_inst === freechips.rocketchip.rocket.Instructions.JALR) && GetRd(e_inst) === RA
}

def IsReturn(inst: UInt)(implicit p: Parameters): Bool =
{
val rvc_exp = Module(new freechips.rocketchip.rocket.RVCExpander)
rvc_exp.io.in := inst
val e_inst = Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
GetUop(e_inst) === jalr_opc && GetRs1(e_inst) === BitPat("b00?01")
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}

// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt =
{
val rvc_exp = Module(new freechips.rocketchip.rocket.RVCExpander)
rvc_exp.io.in := inst
val e_inst = Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
val b_imm32 = Cat(Fill(20,e_inst(31)), e_inst(7), e_inst(30,25), e_inst(11,8), 0.U(1.W))
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}

// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt =
{
val rvc_exp = Module(new freechips.rocketchip.rocket.RVCExpander)
rvc_exp.io.in := inst
val e_inst = Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
val j_imm32 = Cat(Fill(12,e_inst(31)), e_inst(19,12), e_inst(20), e_inst(30,25), e_inst(24,21), 0.U(1.W))
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}

// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt =
{
val bdecode = Module(new boom.exu.BranchDecode)
Expand Down
16 changes: 6 additions & 10 deletions src/main/scala/exu/decode.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -532,6 +532,7 @@ class DecodeUnit(implicit p: Parameters) extends BoomModule()(p)
/**
* Smaller Decode unit for the Frontend to decode different
* branches.
* Accepts EXPANDED RVC instructions
*/

class BranchDecode(implicit p: Parameters) extends BoomModule
Expand All @@ -549,12 +550,8 @@ class BranchDecode(implicit p: Parameters) extends BoomModule
val cfi_type = Output(UInt(CfiType.SZ.W))
})


val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := io.inst
val inst = Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, io.inst)
val bpd_csignals =
freechips.rocketchip.rocket.DecodeLogic(inst,
freechips.rocketchip.rocket.DecodeLogic(io.inst,
List[BitPat](N, N, N, IS_X),
//// // is br?
//// // | is jal?
Expand All @@ -577,12 +574,11 @@ class BranchDecode(implicit p: Parameters) extends BoomModule
io.is_br := cs_is_br
io.is_jal := cs_is_jal
io.is_jalr := cs_is_jalr
io.is_call := (cs_is_jal || cs_is_jalr) && GetRd(inst) === RA
io.is_ret := cs_is_jalr && GetRs1(inst) === BitPat("b00?01")
io.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA
io.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01")

val b_imm32 = Cat(Fill(20,inst(31)),inst(7),inst(30,25),inst(11,8),0.U(1.W))
val j_imm32 = Cat(Fill(12,inst(31)),inst(19,12),inst(20),inst(30,25),inst(24,21),0.U(1.W))
io.target := ((io.pc.asSInt + Mux(cs_is_br, b_imm32, j_imm32).asSInt).asSInt & (-2).S).asUInt
io.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen),
ComputeJALTarget(io.pc, io.inst, xLen))
io.cfi_type :=
Mux(cs_is_jalr,
CfiType.jalr,
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/exu/rob.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -658,7 +658,7 @@ class Rob(
// This should be handled by the front-end.
when ((io.enq_uops(idx).uopc === uopJAL) && !io.enq_uops(idx).exc_cause.orR)
{
r_xcpt_badvaddr := ComputeJALTarget(io.enq_uops(idx).pc, io.enq_uops(idx).inst, xLen)
r_xcpt_badvaddr := ComputeJALTarget(io.enq_uops(idx).pc, ExpandRVC(io.enq_uops(idx).inst), xLen)
}
}
}
Expand Down
6 changes: 3 additions & 3 deletions src/main/scala/ifu/fetch-control-unit.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -303,7 +303,7 @@ class FetchControlUnit(fetch_width: Int)(implicit p: Parameters) extends BoomMod
+ (i << log2Ceil(coreInstBytes)).U
- Mux(use_prev && (i == 0).B, 2.U, 0.U))

bpd_decoder.io.inst := inst
bpd_decoder.io.inst := ExpandRVC(inst)
bpd_decoder.io.pc := pc

f3_valid_mask(i) := f3_valid && f3_imemresp.mask(i) && is_valid
Expand Down Expand Up @@ -686,7 +686,7 @@ class FetchControlUnit(fetch_width: Int)(implicit p: Parameters) extends BoomMod
!f3_fetch_bundle.xcpt_ae_if)
{
assert (f3_fetch_bundle.mask =/= 0.U)
val curr_inst = if (fetchWidth == 1) f3_fetch_bundle.insts(0) else f3_fetch_bundle.insts(cfi_idx)
val curr_inst = ExpandRVC(if (fetchWidth == 1) f3_fetch_bundle.insts(0) else f3_fetch_bundle.insts(cfi_idx))
last_valid := true.B
last_pc := cfi_pc
last_nextlinepc := nextFetchStart(curr_aligned_pc)
Expand Down Expand Up @@ -756,7 +756,7 @@ class FetchControlUnit(fetch_width: Int)(implicit p: Parameters) extends BoomMod
// check that, if there is a jal, the last valid instruction is not after him.
// <beq, jal, bne, ...>, either the beq or jal may be the last instruction, but because
// the jal dominates everything after it, nothing valid can be after it.
val f3_is_jal = VecInit(f3_fetch_bundle.insts map (GetCfiType(_) === CfiType.jal)).asUInt & f3_fetch_bundle.mask
val f3_is_jal = VecInit(f3_fetch_bundle.insts map {x => GetCfiType(ExpandRVC(x)) === CfiType.jal}).asUInt & f3_fetch_bundle.mask
val f3_jal_idx = PriorityEncoder(f3_is_jal)
val has_jal = f3_is_jal.orR

Expand Down
17 changes: 9 additions & 8 deletions src/main/scala/ifu/fetch-monitor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -90,11 +90,12 @@ class FetchMonitor(implicit p: Parameters) extends BoomModule()(p)
prev_valid = uop.valid && io.fire
prev_pc = uop.pc
prev_npc = prev_pc + Mux(uop.is_rvc, 2.U, 4.U)
prev_cfitype = GetCfiType(uop.inst)
val inst = ExpandRVC(uop.inst)
prev_cfitype = GetCfiType(inst)
prev_target =
Mux(prev_cfitype === CfiType.jal,
ComputeJALTarget(uop.pc, uop.inst, xLen),
ComputeBranchTarget(uop.pc, uop.inst, xLen))
ComputeJALTarget(uop.pc, inst, xLen),
ComputeBranchTarget(uop.pc, inst, xLen))
}

// Check if the enqueue'd PC is a target of the previous valid enqueue'd PC.
Expand All @@ -119,18 +120,18 @@ class FetchMonitor(implicit p: Parameters) extends BoomModule()(p)
val end_uop = io.uops(end_idx)
val end_pc = end_uop.pc
val end_compressed = end_uop.inst(1,0) =/= 3.U && usingCompressed.B

val inst = ExpandRVC(end_uop.inst)
last_pc := end_pc
when (end_compressed) {
last_npc := end_pc + 2.U
} .otherwise {
last_npc := end_pc + 4.U
}
last_cfitype := GetCfiType(end_uop.inst)
last_cfitype := GetCfiType(inst)
last_target :=
Mux(GetCfiType(end_uop.inst) === CfiType.jal,
ComputeJALTarget(end_uop.pc, end_uop.inst, xLen),
ComputeBranchTarget(end_uop.pc, end_uop.inst, xLen))
Mux(GetCfiType(inst) === CfiType.jal,
ComputeJALTarget(end_uop.pc, inst, xLen),
ComputeBranchTarget(end_uop.pc, inst, xLen))

when (last_valid)
{
Expand Down

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