Merge pull request #387 from riscv-boom/defunify

Disallow UnifiedMemInt issue queues
riscv-boom · Sep 24, 2019 · ca8a670 · ca8a670
2 parents 783b936 + 8644812
commit ca8a670
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Showing 11 changed files with 32 additions and 62 deletions.
diff --git a/.circleci/config.yml b/.circleci/config.yml
@@ -203,7 +203,7 @@ jobs:
                 key: smallboomandrocketconfig-{{ .Branch }}-{{ .Revision }}
                 paths:
                     - "/home/riscvuser/chipyard"
-    prepare-smallrv32unifiedboomconfig:
+    prepare-smallrv32boomconfig:
         docker:
             - image: riscvboom/riscvboom-images:0.0.10
         environment:
@@ -224,11 +224,11 @@ jobs:
                 keys:
                     - verilator-v12-{{ checksum "CHIPYARD.hash" }}
             - run:
-                name: Building SmallRV32UnifiedBoomConfig using Verilator
-                command: .circleci/do-rtl-build.sh rv32unifiedboom
+                name: Building SmallRV32BoomConfig using Verilator
+                command: .circleci/do-rtl-build.sh rv32boom
                 no_output_timeout: 120m
             - save_cache:
-                key: smallrv32unifiedboomconfig-{{ .Branch }}-{{ .Revision }}
+                key: smallrv32boomconfig-{{ .Branch }}-{{ .Revision }}
                 paths:
                     - "/home/riscvuser/chipyard"
     smallboomconfig-run-csmith-tests:
@@ -437,7 +437,7 @@ jobs:
             - run:
                 name: Run SmallBoomAndRocketConfig riscv tests
                 command: .circleci/run-tests.sh boomandrocket
-    smallrv32unifiedboomconfig-run-csmith-tests:
+    smallrv32boomconfig-run-csmith-tests:
         docker:
             - image: riscvboom/riscvboom-images:0.0.10
         environment:
@@ -450,15 +450,15 @@ jobs:
                     - riscv-tools-installed-v4-{{ checksum "CHIPYARD.hash" }}
             - restore_cache:
                 keys:
-                    - smallrv32unifiedboomconfig-{{ .Branch }}-{{ .Revision }}
+                    - smallrv32boomconfig-{{ .Branch }}-{{ .Revision }}
             - restore_cache:
                 keys:
                     - verilator-v12-{{ checksum "CHIPYARD.hash" }}
             - run:
-                name: Run SmallRV32UnifiedBoomConfig csmith tests
-                command: .circleci/build-run-csmith-tests.sh rv32unifiedboom 50
+                name: Run SmallRV32BoomConfig csmith tests
+                command: .circleci/build-run-csmith-tests.sh rv32boom 50
                 no_output_timeout: 30m
-    smallrv32unifiedboomconfig-run-riscv-tests:
+    smallrv32boomconfig-run-riscv-tests:
         docker:
             - image: riscvboom/riscvboom-images:0.0.10
         environment:
@@ -471,13 +471,13 @@ jobs:
                     - riscv-tools-installed-v4-{{ checksum "CHIPYARD.hash" }}
             - restore_cache:
                 keys:
-                    - smallrv32unifiedboomconfig-{{ .Branch }}-{{ .Revision }}
+                    - smallrv32boomconfig-{{ .Branch }}-{{ .Revision }}
             - restore_cache:
                 keys:
                     - verilator-v12-{{ checksum "CHIPYARD.hash" }}
             - run:
-                name: Run SmallRV32UnifiedBoomConfig riscv tests
-                command: .circleci/run-tests.sh rv32unifiedboom
+                name: Run SmallRV32BoomConfig riscv tests
+                command: .circleci/run-tests.sh rv32boom
 
 # Order and dependencies of jobs to run
 workflows:
@@ -514,7 +514,7 @@ workflows:
                 requires:
                     - prepare-build-environment
                     - install-riscv-tools
-            - prepare-smallrv32unifiedboomconfig:
+            - prepare-smallrv32boomconfig:
                 requires:
                     - prepare-build-environment
                     - install-riscv-tools
@@ -559,7 +559,7 @@ workflows:
                 requires:
                     - prepare-smallboomandrocketconfig
 
-            # Run the SmallRV32UnifiedBoomConfig tests
-            - smallrv32unifiedboomconfig-run-riscv-tests:
+            # Run the SmallRV32BoomConfig tests
+            - smallrv32boomconfig-run-riscv-tests:
                 requires:
-                    - prepare-smallrv32unifiedboomconfig
+                    - prepare-smallrv32boomconfig
diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh
@@ -41,4 +41,4 @@ mapping["mediumboom"]="CONFIG=MediumBoomConfig"
 mapping["largeboom"]="CONFIG=LargeBoomConfig"
 mapping["megaboom"]="CONFIG=MegaBoomConfig"
 mapping["boomandrocket"]="CONFIG=SmallBoomAndRocketConfig"
-mapping["rv32unifiedboom"]="CONFIG=SmallRV32UnifiedBoomConfig"
+mapping["rv32boom"]="CONFIG=SmallRV32BoomConfig"
diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh
@@ -40,7 +40,7 @@ case $1 in
     boomandrocket)
         run_both ${mapping[$1]}
         ;;
-    rv32unifiedboom)
+    rv32boom)
         run_asm ${mapping[$1]}
         ;;
     *)

diff --git a/CHIPYARD.hash b/CHIPYARD.hash
@@ -1 +1 @@
-64d2783b5f0a3d89cb31143fdd5863f0146ec40d
+26042b682c8041b556ff5d83cd340242fbce12f6
diff --git a/src/main/scala/common/config-mixins.scala b/src/main/scala/common/config-mixins.scala
@@ -39,19 +39,6 @@ class WithBoomRV32 extends Config((site, here, up) => {
   }
 })
 
-/**
- * Combines the Memory and Integer Issue Queues. Similar to BOOM v1.
- */
-class WithUnifiedMemIntIQs extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey, site) map { b =>
-    b.copy(core = b.core.copy(
-      issueParams = b.core.issueParams.filter(_.iqType != IQT_MEM.litValue)
-                      .map(iq => if (iq.iqType == IQT_INT.litValue && iq.issueWidth < b.core.decodeWidth)
-                                   iq.copy(issueWidth=b.core.decodeWidth) else iq)
-    ))
-  }
-})
-
 /**
  * Disable support for C-extension (RVC)
  */

diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
@@ -178,15 +178,14 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
 
   val issueParams: Seq[IssueParams] = boomParams.issueParams
   val enableAgePriorityIssue = boomParams.enableAgePriorityIssue
-  val usingUnifiedMemIntIQs = issueParams.count(_.iqType == IQT_MEM.litValue) == 0
 
   // currently, only support one of each.
   require (issueParams.count(_.iqType == IQT_FP.litValue) == 1 || !usingFPU)
-  require (issueParams.count(_.iqType == IQT_MEM.litValue) == 1 || usingUnifiedMemIntIQs)
+  require (issueParams.count(_.iqType == IQT_MEM.litValue) == 1)
   require (issueParams.count(_.iqType == IQT_INT.litValue) == 1)
 
   val intWidth = issueParams.find(_.iqType == IQT_INT.litValue).get.issueWidth
-  val memWidth = if (usingUnifiedMemIntIQs) 1 else issueParams.find(_.iqType == IQT_MEM.litValue).get.issueWidth
+  val memWidth = issueParams.find(_.iqType == IQT_MEM.litValue).get.issueWidth
 
   issueParams.map(x => require(x.dispatchWidth <= coreWidth && x.dispatchWidth > 0))
 

diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -758,7 +758,7 @@ class BoomCore(implicit p: Parameters) extends BoomModule
   issue_units.map(_.io.flush_pipeline := rob.io.flush.valid)
 
   // Load-hit Misspeculations
-  require (issue_units.count(_.iqType == IQT_MEM.litValue) == 1 || usingUnifiedMemIntIQs)
+  require (issue_units.count(_.iqType == IQT_MEM.litValue) == 1)
   val mem_iq = issue_units.mem_iq
 
   require (mem_iq.issueWidth <= 2)

diff --git a/src/main/scala/exu/decode.scala b/src/main/scala/exu/decode.scala
@@ -515,9 +515,6 @@ class DecodeUnit(implicit p: Parameters) extends BoomModule
 
   uop.uopc       := cs.uopc
   uop.iq_type    := cs.iq_type
-  if (usingUnifiedMemIntIQs) {
-    when (cs.iq_type === IQT_MEM) { uop.iq_type := IQT_INT }
-  }
   uop.fu_code    := cs.fu_code
 
   // x-registers placed in 0-31, f-registers placed in 32-63.

diff --git a/src/main/scala/exu/execution-units/execution-unit.scala b/src/main/scala/exu/execution-units/execution-unit.scala
@@ -383,7 +383,7 @@ class ALUExeUnit(
 
   // Mem Unit --------------------------
   if (hasMem) {
-    require(!hasAlu || usingUnifiedMemIntIQs)
+    require(!hasAlu)
     val maddrcalc = Module(new MemAddrCalcUnit)
     maddrcalc.io.req        <> io.req
     maddrcalc.io.req.valid  := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM)

diff --git a/src/main/scala/exu/execution-units/execution-units.scala b/src/main/scala/exu/execution-units/execution-units.scala
@@ -109,18 +109,15 @@ class ExecutionUnits(val fpu: Boolean)(implicit val p: Parameters) extends HasBo
   if (!fpu) {
     val int_width = issueParams.find(_.iqType == IQT_INT.litValue).get.issueWidth
 
-    if (!usingUnifiedMemIntIQs) {
-      for (w <- 0 until memWidth) {
-        val memExeUnit = Module(new ALUExeUnit(
-          hasAlu = false,
-          hasMem = true))
+    for (w <- 0 until memWidth) {
+      val memExeUnit = Module(new ALUExeUnit(
+        hasAlu = false,
+        hasMem = true))
 
-        memExeUnit.io.ll_iresp.ready := DontCare
+      memExeUnit.io.ll_iresp.ready := DontCare
 
-        exe_units += memExeUnit
-      }
+      exe_units += memExeUnit
     }
-    require(!(usingUnifiedMemIntIQs && memWidth != 1))
 
     for (w <- 0 until int_width) {
       def is_nth(n: Int): Boolean = w == ((n) % int_width)
@@ -130,8 +127,7 @@ class ExecutionUnits(val fpu: Boolean)(implicit val p: Parameters) extends HasBo
         hasRocc        = is_nth(1) && usingRoCC,
         hasMul         = is_nth(2),
         hasDiv         = is_nth(3),
-        hasIfpu        = is_nth(4) && usingFPU,
-        hasMem         = is_nth(0) && usingUnifiedMemIntIQs))
+        hasIfpu        = is_nth(4) && usingFPU))
       exe_units += alu_exe_unit
     }
   } else {

diff --git a/src/main/scala/exu/issue-units/issue-units.scala b/src/main/scala/exu/issue-units/issue-units.scala
@@ -58,11 +58,7 @@ class IssueUnits(val numWakeupPorts: Int)(implicit val p: Parameters)
 
     // name the issue units
     if (issueParam.iqType == IQT_INT.litValue) {
-      if (usingUnifiedMemIntIQs) {
-        issue_unit.suggestName("intmem_issue_unit")
-      } else {
-        issue_unit.suggestName("int_issue_unit")
-      }
+      issue_unit.suggestName("int_issue_unit")
     } else if (issueParam.iqType == IQT_MEM.litValue) {
       issue_unit.suggestName("mem_issue_unit")
     }
@@ -75,12 +71,7 @@ class IssueUnits(val numWakeupPorts: Int)(implicit val p: Parameters)
    *
    * @return the IssueUnit used for memory uops
    */
-  def mem_iq = if (usingUnifiedMemIntIQs) {
-    // When using unified issue queues the IQT_INT handles everything
-    issue_units.find(_.iqType == IQT_INT.litValue).get
-  } else {
-    issue_units.find(_.iqType == IQT_MEM.litValue).get
-  }
+  def mem_iq = issue_units.find(_.iqType == IQT_MEM.litValue).get
 
   /**
    * Get the integer issue queue