[rv32] Cleanup for merge

riscv-boom · Jan 27, 2019 · d1b184e · d1b184e
1 parent bf6951a
commit d1b184e
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/src/main/scala/common/consts.scala b/src/main/scala/common/consts.scala
@@ -23,7 +23,7 @@ import freechips.rocketchip.util.Str
 trait BOOMDebugConstants
 {
    val DEBUG_PRINTF        = false // use the Chisel printf functionality
-   val COMMIT_LOG_PRINTF   = true // dump commit state, for comparision against ISA sim
+   val COMMIT_LOG_PRINTF   = false // dump commit state, for comparision against ISA sim
    val O3PIPEVIEW_PRINTF   = false // dump trace for O3PipeView from gem5
    val O3_CYCLE_TIME       = (1000)// "cycle" time expected by o3pipeview.py
 

diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
@@ -126,7 +126,7 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
    val usingFDivSqrt = boomParams.fpu.isDefined && boomParams.fpu.get.divSqrt
 
    val mulDivParams = boomParams.mulDiv.getOrElse(MulDivParams())
-   // TODO: Allow this
+   // TODO: Allow RV32IF
    require(!(xLen == 32 && usingFPU), "RV32 does not support fp")
 
    //************************************

diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
@@ -27,7 +27,7 @@ class BoomConfig extends Config(
    new DefaultBoomConfig ++
    new WithNBoomCores(1) ++
    new WithoutTLMonitors ++
-      new freechips.rocketchip.system.BaseConfig)
+   new freechips.rocketchip.system.BaseConfig)
 
 // Main configs. SmallBoomConfig and MediumBoomConfig are best-maintained
 // MediumBoomConfig is typically described in documentation