Merge pull request #486 from riscv-boom/fix-debug-mode

[exu] Flush the ICache on a debug-mode JALR, to work around caching the uncacheable debug ram
riscv-boom · Aug 27, 2020 · f69eac8 · f69eac8
2 parents c04a406 + c1ba5e3
commit f69eac8
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -377,7 +377,9 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
   io.ifu.bp      := csr.io.bp
 
   io.ifu.flush_icache := (0 until coreWidth).map { i =>
-    rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei }.reduce(_||_)
+    (rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) ||
+    (dec_uops(i).is_jalr && csr.io.status.debug)
+  }.reduce(_||_)
 
   // TODO FIX THIS HACK
   // The below code works because of two quirks with the flush mechanism