Merge pull request #358 from riscv-boom/deprecate-old-fb

[ifu] Deprecate the old FetchBuffer.
riscv-boom · Jul 27, 2019 · f9499c7 · f9499c7
2 parents e672f92 + 8cf76f0
commit f9499c7
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Showing 4 changed files with 2 additions and 258 deletions.
diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
@@ -39,7 +39,6 @@ case class BoomCoreParams(
   enableCustomRfModel: Boolean = true,
   maxBrCount: Int = 4,
   numFetchBufferEntries: Int = 16,
-  useNewFetchBuffer: Boolean = true,
   enableAgePriorityIssue: Boolean = true,
   enablePrefetching: Boolean = false,
   enableBrResolutionRegister: Boolean = true,
@@ -158,7 +157,6 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
   val maxBrCount    = boomParams.maxBrCount          // number of branches we can speculate simultaneously
   val ftqSz         = boomParams.ftq.nEntries        // number of FTQ entries
   val numFetchBufferEntries = boomParams.numFetchBufferEntries // number of instructions that stored between fetch&decode
-  val useNewFetchBuffer = boomParams.useNewFetchBuffer
 
   val numIntPhysRegs= boomParams.numIntPhysRegisters // size of the integer physical register file
   val numFpPhysRegs = boomParams.numFpPhysRegisters  // size of the floating point physical register file

diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -441,8 +441,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
   dec_fire := (0 until coreWidth).map(w => dec_valids(w) && !dec_stalls(w))
 
   // all decoders are empty and ready for new instructions
-  if (useNewFetchBuffer) dec_ready := dec_fire.last
-  else                   dec_ready := !dec_stalls.last
+  dec_ready := dec_fire.last
 
   when (dec_ready || flush_ifu) {
     dec_finished_mask := 0.U

diff --git a/src/main/scala/ifu/fetch-control-unit.scala b/src/main/scala/ifu/fetch-control-unit.scala
@@ -116,8 +116,7 @@ class FetchControlUnit(implicit p: Parameters) extends BoomModule
 
   val bchecker = Module (new BranchChecker)
   val ftq = Module(new FetchTargetQueue(num_entries = ftqSz))
-  val fb = if (useNewFetchBuffer) Module(new    FetchBuffer(numEntries=numFetchBufferEntries))
-           else                   Module(new OldFetchBuffer(numEntries=1<<log2Ceil(numFetchBufferEntries)))
+  val fb  = Module(new FetchBuffer(numEntries=numFetchBufferEntries))
   val monitor: Option[FetchMonitor] = (useFetchMonitor).option(Module(new FetchMonitor))
 
   val br_unit = io.br_unit

diff --git a/src/main/scala/ifu/old-fetch-buffer.scala b/src/main/scala/ifu/old-fetch-buffer.scala