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DCache prefetching + multi-issue #366

Merged
merged 54 commits into from
Sep 16, 2019
Merged

DCache prefetching + multi-issue #366

merged 54 commits into from
Sep 16, 2019

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jerryz123
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@jerryz123 jerryz123 commented Aug 6, 2019 •
edited

  • LineBuffer acts as prefetch buffer
  • DTLB is multi-ported
  • LSU/DCache can handle 2-loads/1-store per cycle
  • DCache has configurable banking of data arrays (thanks @bkorpan)

jerryz123 and others added 24 commits August 11, 2019 22:52
@jerryz123
[dcache] Simplify non-prefetch line-buffer
af03e5d
@jerryz123
[prefetch] Don't try to prefetch from invalid regions
644f087
@jerryz123
[tlb] Dual-port the DTLB
41c7f48
@jerryz123
[lsu] Attempt at multi-porting cache
7d5fd49
@jerryz123
[lsu] Fixes for multi-issue LSU
3ea32b8
@jerryz123
[lsu] Allow loads executing in parallel to not interfere with each other
c395958
@jerryz123
[lsu] Fix branch kills for dual-issue LSU
34a640b
@jerryz123
[lsu] Don't allow sta_retry and std_incoming fire together for the sa…
960127e 
…me store
@jerryz123
[dcache] Fix linebuffer usage when prefetching
e4141af
@jerryz123
[dcache] Don't throw LD-LD failures if the cache state was not observed
3a5b5c7
@jerryz123
[iss] Allow priorization of branches at issue
310ba5b
@bkorpan
[lsu] Copy DataArray to dcache.
b57a472
@bkorpan
[common] Added numDCacheBanks BoomCoreParam.
092e2f2
@bkorpan
[lsu] Removed generator for doNarrowRead.
bcd95ee
@bkorpan
[lsu] Use chisel3 syntax.
46a76ee
@bkorpan
[lsu] Multiported BoomDataArray interface.
ea69117
@bkorpan
[lsu] Instantiate banks.
c864626
@bkorpan
[lsu] Properly compute size of bank SRAMs.
d181c3f
@bkorpan
[lsu] Generate read/write bank indices.
804d915
@bkorpan
[lsu] Generate bank grant signasl.
da3cbf9
@bkorpan
[lsu] Use bank grants to hookup array reads/writes.
0ae3e9e
@bkorpan
[lsu] Add nacks signal to DataArray.
b2a78c8
@bkorpan
[lsu] Add stage names to BoomDataArray signals.
02d3a10
@bkorpan
[lsu] Allow for read sharing when a conflicting access requests the s…
1cf95ac 
…ame bank row.
bkorpan and others added 10 commits August 25, 2019 14:25
@jerryz123 jerryz123 changed the base branch from dcache3 to master August 31, 2019 04:30
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jerryz123 commented Sep 16, 2019 •
edited

MegaBoom + L2 + dual-issue mem booted Fedora, merging

@jerryz123 jerryz123 merged commit f6ffb9c into master Sep 16, 2019
@jerryz123 jerryz123 deleted the dcache3-prefetch branch September 19, 2019 23:42
@jerryz123 jerryz123 restored the dcache3-prefetch branch September 19, 2019 23:42
@jerryz123 jerryz123 deleted the dcache3-prefetch branch February 26, 2020 21:16
@jerryz123 jerryz123 restored the dcache3-prefetch branch February 26, 2020 21:16
@jerryz123 jerryz123 deleted the dcache3-prefetch branch May 27, 2020 18:03
jerryz123 added a commit that referenced this pull request Mar 11, 2021
@jerryz123
Do not check that chisel3 and firrtl submodule branches are whitelist…
4d58321 
…ed (#366)

Chisel3 and FIRRTL use release branches, which we track instead.
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