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Ultrawide Core Fixes #476

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Ultrawide Core Fixes #476

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3468363
Add TeraBoomConfig | increase max meta size (is there a way to do thi…
bkorpan Jul 18, 2020
3d79abe
Remove memWidth<=2 requirement
bkorpan Jul 18, 2020
cbdc4e8
Fix req_idx calculation
bkorpan Jul 18, 2020
9cb4d68
Rejigger memory port assignment (main thing is to put store commits o…
bkorpan Jul 18, 2020
ea1332b
Don't need that many branch slots.
bkorpan Jul 19, 2020
1152672
Make commit log match spike formatting
bkorpan Jul 21, 2020
dd5a238
Rework LR/SC logic to allow the (memWidth-1)'th pipe to zero the coun…
bkorpan Jul 21, 2020
a19dd1a
Allow a probe to come from any pipe
bkorpan Jul 22, 2020
db51f04
Can't do that if memWidth == 1.
bkorpan Jul 22, 2020
760fa8b
Move wakeup pipe
bkorpan Jul 25, 2020
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105 changes: 100 additions & 5 deletions src/main/scala/common/config-mixins.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,7 @@ class WithNSmallBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
numFpPhysRegisters = 48,
numLdqEntries = 8,
numStqEntries = 8,
maxBrCount = 8,
maxBrCount = 4,
numFetchBufferEntries = 8,
ftq = FtqParameters(nEntries=16),
nPerfCounters = 2,
Expand Down Expand Up @@ -150,7 +150,7 @@ class WithNMediumBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
numFpPhysRegisters = 64,
numLdqEntries = 16,
numStqEntries = 16,
maxBrCount = 12,
maxBrCount = 8,
numFetchBufferEntries = 16,
ftq = FtqParameters(nEntries=32),
nPerfCounters = 6,
Expand Down Expand Up @@ -197,7 +197,7 @@ class WithNLargeBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends
numFpPhysRegisters = 96,
numLdqEntries = 24,
numStqEntries = 24,
maxBrCount = 16,
maxBrCount = 12,
numFetchBufferEntries = 24,
ftq = FtqParameters(nEntries=32),
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
Expand Down Expand Up @@ -244,7 +244,7 @@ class WithNMegaBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends C
numFpPhysRegisters = 128,
numLdqEntries = 32,
numStqEntries = 32,
maxBrCount = 20,
maxBrCount = 16,
numFetchBufferEntries = 32,
enablePrefetching = true,
ftq = FtqParameters(nEntries=40),
Expand Down Expand Up @@ -315,6 +315,101 @@ class WithNGigaBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends C
})
)

/**
* 8-wide BOOM.
*/
class WithNTeraBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = overrideIdOffset.getOrElse(prev.size)
(0 until n).map { i =>
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 16,
decodeWidth = 8,
numRobEntries = 256,
issueParams = Seq(
IssueParams(issueWidth=3, numEntries=36, iqType=IQT_MEM.litValue, dispatchWidth=8),
IssueParams(issueWidth=6, numEntries=64, iqType=IQT_INT.litValue, dispatchWidth=8),
IssueParams(issueWidth=3, numEntries=32, iqType=IQT_FP.litValue , dispatchWidth=8)),
numIntPhysRegisters = 256,
numFpPhysRegisters = 144,
numLdqEntries = 64,
numStqEntries = 64,
maxBrCount = 32,
numFetchBufferEntries = 64,
enablePrefetching = true,
numDCacheBanks = 1,
ftq = FtqParameters(nEntries=32),
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=16, nMSHRs=8, nTLBEntries=32)
),
icache = Some(
ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=16, fetchBytes=4*8)
),
hartId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16)
case XLen => 64
})
)

/**
* 10-wide BOOM.
*/
class WithNPetaBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = overrideIdOffset.getOrElse(prev.size)
(0 until n).map { i =>
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 16,
decodeWidth = 10,
numRobEntries = 320,
issueParams = Seq(
IssueParams(issueWidth=5 , numEntries=50 , iqType=IQT_MEM.litValue, dispatchWidth=10),
IssueParams(issueWidth=10, numEntries=100, iqType=IQT_INT.litValue, dispatchWidth=10),
IssueParams(issueWidth=8 , numEntries=80 , iqType=IQT_FP.litValue , dispatchWidth=10)),
numIntPhysRegisters = 256,
numFpPhysRegisters = 256,
numLdqEntries = 64,
numStqEntries = 64,
maxBrCount = 40,
numFetchBufferEntries = 100,
enablePrefetching = true,
numDCacheBanks = 1,
ftq = FtqParameters(nEntries=40),
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=16, nMSHRs=8, nTLBEntries=32)
),
icache = Some(
ICacheParams(rowBits = site(SystemBusKey).beatBits, nSets=64, nWays=16, fetchBytes=4*8)
),
hartId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16)
case XLen => 64
})
)
/**
* BOOM Configs for CS152 lab
*/
Expand Down Expand Up @@ -424,7 +519,7 @@ class WithNCS152DefaultBooms(n: Int = 1, overrideIdOffset: Option[Int] = None) e
class WithTAGELBPD extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
bpdMaxMetaLength = 120,
bpdMaxMetaLength = 221,
globalHistoryLength = 64,
localHistoryLength = 1,
localHistoryNSets = 0,
Expand Down
42 changes: 33 additions & 9 deletions src/main/scala/exu/core.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -936,7 +936,6 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
issue_units.map(_.io.flush_pipeline := RegNext(rob.io.flush.valid))

// Load-hit Misspeculations
require (mem_iss_unit.issueWidth <= 2)
issue_units.map(_.io.ld_miss := io.lsu.ld_miss)

mem_units.map(u => u.io.com_exception := RegNext(rob.io.flush.valid))
Expand Down Expand Up @@ -1320,12 +1319,10 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule


if (COMMIT_LOG_PRINTF) {
var new_commit_cnt = 0.U

for (w <- 0 until coreWidth) {
val priv = RegNext(csr.io.status.prv) // erets change the privilege. Get the old one

// To allow for diffs against spike :/
// To allow for diffs against spike
def printf_inst(uop: MicroOp) = {
when (uop.is_rvc) {
printf("(0x%x)", uop.debug_inst(15,0))
Expand All @@ -1334,19 +1331,46 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
}
}

when (rob.io.commit.arch_valids(w)) {
io.lsu.debug_stcom(w).idx := rob.io.commit.uops(w).stq_idx

when (rob.io.commit.valids(w)) {
val com_uop = rob.io.commit.uops(w)
printf("%d 0x%x ",
priv,
Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))
Sext(com_uop.debug_pc(vaddrBits-1,0), xLen))
printf_inst(rob.io.commit.uops(w))
when (rob.io.commit.uops(w).dst_rtype === RT_FIX && rob.io.commit.uops(w).ldst =/= 0.U) {
when (com_uop.dst_rtype === RT_FIX && com_uop.ldst =/= 0.U) {
printf(" x%d 0x%x\n",
rob.io.commit.uops(w).ldst,
com_uop.ldst,
rob.io.commit.debug_wdata(w))
} .elsewhen (rob.io.commit.uops(w).dst_rtype === RT_FLT) {
printf(" f%d 0x%x\n",
rob.io.commit.uops(w).ldst,
com_uop.ldst,
rob.io.commit.debug_wdata(w))
} .elsewhen (com_uop.uses_stq && !com_uop.is_fence) {
val stq_data = io.lsu.debug_stcom(w).data
val mem_size = com_uop.mem_size
when (mem_size === 3.U) {
printf(" mem 0x%x 0x%x\n",
io.lsu.debug_stcom(w).addr,
stq_data)
} .elsewhen (mem_size === 2.U) {
printf(" mem 0x%x 0x%x\n",
io.lsu.debug_stcom(w).addr,
stq_data(31,0))
} .elsewhen (mem_size === 1.U) {
printf(" mem 0x%x 0x%x\n",
io.lsu.debug_stcom(w).addr,
stq_data(15,0))
} .elsewhen (stq_data(7,4).orR) {
printf(" mem 0x%x 0x%x\n",
io.lsu.debug_stcom(w).addr,
stq_data(7,0))
} .otherwise { // Drop leading zero from byte stores to match a bug in spike
printf(" mem 0x%x 0x%x\n",
io.lsu.debug_stcom(w).addr,
stq_data(3,0))
}
} .otherwise {
printf("\n")
}
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/ifu/bpd/composer.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ class ComposedBranchPredictorBank(implicit p: Parameters) extends BranchPredicto
}
meta_sz = meta_sz + c.metaSz
}
require(meta_sz < bpdMaxMetaLength)
require(meta_sz <= bpdMaxMetaLength)
io.f3_meta := metas


Expand Down
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