Ztso psABI atomics specification #391
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@hboehm @kito-cheng @jrtc27 @ilovepi @nick-knight @asb @enh-google @daniellustig @aparri |
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Is there a reason to present these as an alternate mapping scheme, rather than as additional mappings that are enabled by Ztso? If not, I would prefer the latter presentation, for several reasons:
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To be clear, are you proposing a diff-only table like this?
I did separate mappings since it made it easier for me to verify my implementations were consistent with the table. Regarding point 4: I'm also not enough of an ELF expert, but I know we have a TSO bit allocated in e_flags for Ztso binaries. |
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Indeed. I would prefer the "diff-only" table, noting that it can contain only additions. In my view, mix-and-match is completely unavoidable at the whole application level, so it would be better to be explicit about that in the spec. I also think we are likely to eventually end up with too many combinations to reasonably list all of them in the spec. Compiler writers will have to pick the right combination for the specified target hardware, and for their performance expectations. And we have to convince ourselves that they all play together (with the existing disclaimers about the A.6 mappings). |
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I reformatted the table/reworded some of the surrounding text to make it more clear that these are additional mappings enabled by the Ztso extension. I also changed the wording for the TSO bit to allow linking RVWMO/TSO binaries in a similar way to how RVC binaries are handled. |
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For the atomic flag stuffs, we will need add a |
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The merge result still needs to be marked as Eg. IIUC, the |
My point is TSO mapping is not make sense to set either |
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Is the TSO bit in |
It's less useful, but it provide a way to do faster check for dynamic linker/program loader if needed, and it...allocated for a while, so I tend to keep as it. |
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I would prefer to treat Ztso as a pure ISA extension which allows certain fences to be elided, and have object files which assume Ztso semantics for loads and stores claim conformance to the RVWMO memory models without adding additional complexity to the ATOMIC_ABI selection. |
But TSO mapping (this PR) is not compatible/conformance either IMO that will increase the complexity of ATOMIC_ABI since we also need to consider e_flags.EF_RISCV_TSO when interpreter which atomic mapping are using for the object/executable. |
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According to the diff «All mappings interoperate correctly with the RVWMO mappings, and with the original "Table A.6" mappings.» which means that we should be setting whatever ATOMIC_ABI value is adopted to resolve #385 (comment) . We cannot, in general, assume that object files will conform to any particular ABI if the extensions they depend on are not present; this is true for EF_RISCV_TSO in exactly the same way that it is true for EF_RISCV_RVC. (A vendor could replace the 16-bit encoding space with memory instructions that don't follow RVWMO, and then trying to run an EF_RISCV_RVC object file would result in ATOMIC_ABI violations, but this isn't seen as coupling EF_RISCV_RVC with the ATOMIC_ABI and that doesn't mean that we also need to consider e_flags.EF_RISCV_RVC when interpreting which atomic mapping is used.) |
I agree that the A6C_ATOMIC_ABI + TSO is not capible of running on a non-TSO machine. However, I believe the TSO and *_ATOMIC_ABI are two separate things. The TSO e_flags bit tells you if a binary is capable of running on a RVWMO machine or not. The *_ATOMIC_ABI tells you if two binaries can be safely linked together. A6C and A6S encode the same compatibilities on Ztso or RVWMO machines (as long as you respect when the TSO bit requires Ztso).
The issue is that this PR defines a possible TSO mapping that is not compatible with A6C objects (A Note 3 mapping). Linking a A6C object with a TSO object does not guarantee compatibility, so just marking the resulting binary as TSO_ATOMIC_ABI isn't a valid solution. I think we need something like Hans' suggestion here regarding an A7_ATOMIC_ABI (Note 3 mappings) which is non-compatible with A6C. Then we can use the TSO bit to declare a binary as TSO (or not), and the 3 *_ATOMIC_ABI states to encode compatibility between those binaries (ignoring the TSO bit) (A6C, A6S, A7). Respecting the *_ATOMIC_ABI is dependent on respecting the TSO bit.
Agreed. |
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I gather there have also been discussions about 8- and 16-bit variants of the AMO operations. If those materialize, that would be another instance in which we would want to extend the mappings in the presence of an ISA extension. I think it would be great if such a future extension could just follow the model we use for Ztso here. |
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I am struggling what is the right merge behavior and what's the meaning of those flags (ATOMIC_ABI and EF_RISCV_TSO), so I trying to write my understanding and enumerate the situation (w/o adding TSO_ATOMIC_ABI and w/ A7_ATOMIC_ABI), please correct me if anything you feel wrong :) EF_RISCV_TSO means the ELF require run on the machine has Ztso extension. We have few objects using different atomic mapping. ATOMIC_ABI + EF_RISCV_TSOSo when no mixing different mapping, those setting would be:
OK, let combination the situation:
ATOMIC_ABI (w/ TSO_ATOMIC_ABI) + EF_RISCV_TSOAnd try to add TSO_ATOMIC_ABI
Two bit scheme (EF_RISCV_ATOMIC_A6/EF_RISCV_ATOMIC_A7)And let me try to using 2 bit scheme which proposed by #383, and we can use similar scheme on ELF attribute if we think it's right way. ATOMIC_A6 = EF_RISCV_ATOMIC_A6
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It may be worth noting that the only thing EF_RISCV_TSO=1 allows you to do is delete fences (and aqrl bits) that are already no-ops on Ztso implementations, which means that it will only marginally help on Ztso implementations that can delete no-ops early in the frontend. My argument is that TSO objects should be marked with the atomic ABI they are compatible with, so for the 2-bit version TSO.o should have all of ATOMIC_A6, ATOMIC_A7, and TSO = 1; for the #385 version TSO.o should have A6S_ATOMIC_ABI and EF_RISCV_TSO=1. |
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I think the Two bit scheme (EF_RISCV_ATOMIC_A6/EF_RISCV_ATOMIC_A7) is the closest table you have to what I was thinking of. The *_TSO mappings have been made with RVWMO compatibility in mind, so the TSO bit can be safely ignored when deciding compatibility (as long as the TSO bit is set if one of the inputs has the TSO bit set). First, the compatibility between UNKNOWN, A6C, A6S, and A7.
Next, the behavior of TSO
Now, because the TSO mappings were created to have the same ABIs and be compatible with RVWMO mappings, we can just combine the two tables:
It's a bit unwieldy but shows all the 2-input states :) Covering some 3 input cases:
Regarding your tables, there are a few entries that I think are incorrect. You can implement an A7 binary today using a note 3 mapping like:
This isn't right since A7 is the more restrictive of the two ABIs, so we should be outputting A7_ATOMIC_ABI. |
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I agree with Patrick. The rules for UNKNOWN might be debatable, since UNKNOWN also applies to old gcc-generated code. But I'm OK with Patrick's argument. If we decompose the ATOMIC_ABI value into an A6C-compatible bit and an A7-compatible bit, treating 00 as UNKNOWN, with A6S = 11, then the ATOMIC_ABI combination rule becomes: If either object file has tag 00 (UNKNOWN), then the result tag is the other one, otherwise That description wins on brevity, I think, but perhaps not on clarity. Either description is fine with me. |
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Thanks for expanding the table, that's really much clear to me, I think what I stuck is I am trying to define/understand ATOMIC_ABI is minimal conformance rather than compatible, so that's why I think A6S + A7 should be A6S_ATOMIC_ABI since I treat A6S_ATOMIC_ABI is less stronger than A7_ATOMIC_ABI. And one last thing I want to make sure is what ATOMIC_ABI should be used if compiler using this TSO mapping? does @sorear's description same as what you think? @patrick-rivos @hboehm @sorear It's really nice discussion here, that fix my server wrong understanding around there :) |
Glad it was helpful. The way I think about it is that A6S is a compatibility mapping, so the general flow when merging ABIs is like this: You can never go back up a level, so merging ABIs will always move you to the lowest level of your inputs. Feel free to ignore this if it's confusing - it's the same as the table, just different way of displaying it. Also please forgive the bad ascii art ;)
Yes @sorear's description is the same as what I was thinking. The compiler should emit A6S_ATOMIC_ABI if no Note3 mappings are used. If Note3 mappings are used then we need to emit A7_ATOMIC_ABI. |
kito-cheng
reviewed
Aug 7, 2023
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@hboehm Do you mind give explicitly LGTM for this if it's OK to you? @patrick-rivos has reach the requirement of the psABI spec change - require either GNU or LLVM implementation, and he did both :P So I intend to merge this change after address those minor comment and if it's OK to you :) |
hboehm
reviewed
Aug 7, 2023
hboehm
reviewed
Aug 7, 2023
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LGTM, whether or not you accept my two minor suggestions above. |
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I think all the feedback has been addressed. LMK if I missed anything :) |
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Please tidy up the commit history |
jrtc27
reviewed
Aug 7, 2023
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Squashed the commits and replaced |
kito-cheng
approved these changes
Aug 8, 2023
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Currently LLVM emits Ztso code for fences, loads, and stores (behind an experimental flag) [1]. This patch updates the mapping and implements support for LR/SC and AMO ops. This updated mapping is compatible with the RVWMO ABI present in the psABI. Additional context can be found in the psABI pull request [2]. [1] https://reviews.llvm.org/D143076 [2] riscv-non-isa/riscv-elf-psabi-doc#391 Differential Revision: https://reviews.llvm.org/D155517
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The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> (cherry picked from commit 0ac3232)
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The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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Mar 13, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Liaoshihua
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Mar 13, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Liaoshihua
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Mar 13, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Liaoshihua
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Mar 15, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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Mar 17, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Liaoshihua
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Mar 19, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Liaoshihua
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Mar 21, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Liaoshihua
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Mar 25, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
XYenChi
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that referenced
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Mar 25, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Liaoshihua
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to Liaoshihua/gcc
that referenced
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Mar 27, 2024
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] riscv-non-isa/riscv-elf-psabi-doc#391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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This PR defines an optimized atomics mapping ABI for Ztso targets. It is a strengthened version of Andrea Parri's proposed Ztso mappings ("Proposed Mapping") [1]. The proposal changes were discussed by Andrea Parri and Hans Boehm on the GCC mailing list [2] and are required in order to be compatible with the RVWMO A.7 ABI (mappings with note 3 in the psABI atomics table).
[1] https://github.com/preames/public-notes/blob/master/riscv-tso-mappings.rst
[2] https://inbox.sourceware.org/gcc-patches/ZFV8pNAstwrF2qBb@andrea/T/#t