[Auto-gen] Update tests under ../auto-generated. (make git-commit-aut…

…ogen-test)
riscv-non-isa · Apr 28, 2023 · e31b553 · e31b553
1 parent 3379a91
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diff --git a/auto-generated/api-testing/vfadd.c b/auto-generated/api-testing/vfadd.c
diff --git a/auto-generated/api-testing/vfcvt.c b/auto-generated/api-testing/vfcvt.c
diff --git a/auto-generated/api-testing/vfcvt_rtz.c b/auto-generated/api-testing/vfcvt_rtz.c
diff --git a/auto-generated/api-testing/vfdiv.c b/auto-generated/api-testing/vfdiv.c
diff --git a/auto-generated/api-testing/vfmacc.c b/auto-generated/api-testing/vfmacc.c
diff --git a/auto-generated/api-testing/vfmadd.c b/auto-generated/api-testing/vfmadd.c
diff --git a/auto-generated/api-testing/vfmsac.c b/auto-generated/api-testing/vfmsac.c
diff --git a/auto-generated/api-testing/vfmsub.c b/auto-generated/api-testing/vfmsub.c
diff --git a/auto-generated/api-testing/vfmul.c b/auto-generated/api-testing/vfmul.c
diff --git a/auto-generated/api-testing/vfncvt.c b/auto-generated/api-testing/vfncvt.c
diff --git a/auto-generated/api-testing/vfncvt_rod.c b/auto-generated/api-testing/vfncvt_rod.c
@@ -76,3 +76,363 @@ vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size
   return __riscv_vfncvt_rod_f_f_w_f32m4_m(mask, src, vl);
 }
 
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2(src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1(src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2(src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1(src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2(src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4(src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4_m(mask, src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2_m(mask, src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1_m(mask, src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2_m(mask, src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4_m(mask, src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2_m(mask, src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1_m(mask, src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2_m(mask, src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4_m(mask, src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2(src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1(src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2(src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1(src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2(src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4(src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4_m(mask, src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2_m(mask, src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1_m(mask, src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2_m(mask, src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4_m(mask, src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2_m(mask, src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1_m(mask, src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2_m(mask, src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4_m(mask, src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2(src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1(src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2(src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1(src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2(src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4(src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4_m(mask, src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2_m(mask, src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1_m(mask, src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2_m(mask, src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4_m(mask, src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2_m(mask, src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1_m(mask, src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2_m(mask, src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4_m(mask, src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2(src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1(src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2(src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1(src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2(src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4(src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4_m(mask, src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2_m(mask, src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1_m(mask, src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2_m(mask, src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4_m(mask, src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2_m(mask, src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1_m(mask, src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2_m(mask, src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4_m(mask, src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2(src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1(src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2(src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1(src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2(src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4(src, vl);
+}
+
+vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf4_m(mask, src, vl);
+}
+
+vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16mf2_m(mask, src, vl);
+}
+
+vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m1_m(mask, src, vl);
+}
+
+vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m2_m(mask, src, vl);
+}
+
+vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f16m4_m(mask, src, vl);
+}
+
+vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32mf2_m(mask, src, vl);
+}
+
+vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m1_m(mask, src, vl);
+}
+
+vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m2_m(mask, src, vl);
+}
+
+vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {
+  return __riscv_vfncvt_rod_f_f_w_f32m4_m(mask, src, vl);
+}
+