Proposal of the intrinsics for vector crypto #234

eopXD · 2023-06-01T12:43:12Z

Update (2023/11/11)

The vector crypto extension is now has a released v1.0.0 [0]. This PR creates intrinsics that exposes interfaces to the vector crypto instructions.

Regarding the data type used in the intrinsics added, this proposal does not model the concept of "element grouping (EGS/EGW)" and reuses the existing data types of the RVV intrinsics (e.g. vuint32m1_t, vuint64m2_t).

The LLVM implementation of the intrinsics is the following: (to be updated to latest v20230531)

D138810 [RISCV] Support vector crypto extension C intrinsics
D138809 [RISCV] Support vector crypto extension LLVM IR

[0] https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0

auto-generated/vector-crypto/api-testing/vwsll.c

...ated/vector-crypto/intrinsic_funcs/00_zvbb_-_vector_bit-manipulation_used_in_cryptography.md

nick-knight · 2023-07-05T15:42:08Z

...ated/vector-crypto/intrinsic_funcs/00_zvbb_-_vector_bit-manipulation_used_in_cryptography.md

+vuint64m8_t __riscv_vror_vx_u64m8_m (vbool8_t mask, vuint64m8_t vs2, uint64_t rs1, size_t vl);
+```
+
+### [Vector Bit-manipulation used in Cryptography - Shift]():


We have signed and unsigned versions of vsll, but this proposal only adds unsigned versions of vwsll. I'm not proposing a change, just mentioning this asymmetry.

Yes I am also aware of the asymmetry. The vector crypto instructions generally operates under an unsigned data type and all other intrinsics does not have variants for signed data type. So I think it is more reasonable to not a signed data type variant here.

vwsll will zero-extend vs2 to 2x SEW, so I think no signed version might be less confused.

auto-generated/vector-crypto/llvm-api-tests/vrol.c

auto-generated/vector-crypto/api-testing/vclmul.c

auto-generated/vector-crypto/api-testing/vsha2c.c

auto-generated/vector-crypto/api-testing/vaeskf1.c

auto-generated/vector-crypto/api-testing/vaeskf2.c

auto-generated/vector-crypto/llvm-api-tests/vaesdf.c

auto-generated/vector-crypto/llvm-api-tests/vaesdm.c

auto-generated/vector-crypto/llvm-api-tests/vaesef.c

auto-generated/vector-crypto/llvm-api-tests/vaesem.c

auto-generated/vector-crypto/llvm-api-tests/vaesz.c

auto-generated/vector-crypto/llvm-api-tests/vclmul.c

auto-generated/vector-crypto/llvm-api-tests/vclmulh.c

auto-generated/vector-crypto/policy_funcs/llvm-api-tests/vclmul.c

auto-generated/vector-crypto/api-testing/vsm3c.c

auto-generated/vector-crypto/api-testing/vsm4k.c

4vtomat · 2023-07-12T06:08:06Z

auto-generated/vector-crypto/llvm-api-tests/vsm4r.c

+}
+
+vuint32mf2_t test_vsm4r_vs_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {
+  return __riscv_vsm4r_vs_u32mf2(vd, vs2, vl);


I think vs2 of .vs type of this instruction should have lmul1 type.

auto-generated/vector-crypto/llvm-overloaded-tests/vsm4r.c

auto-generated/vector-crypto/intrinsic_funcs/01_zvbc_-_vector_carryless_multiplication.md

auto-generated/vector-crypto/intrinsic_funcs/04_zvkned_-_nist_suite:_vector_aes_block_cipher.md

auto-generated/vector-crypto/intrinsic_funcs/05_zvkned_-_nist_suite:_vector_aes_block_cipher.md

eopXD · 2023-07-17T17:45:46Z

Address comments from Craig, Nick, Brandon, and Nicholas. Thank you guys for the review.

Changes:

Zvbb - Vector Bit-manipulation used in Cryptography
Return correct LMUL type for vwsll in the function name suffix
Change rs1 operand to using type size_t

Zvbc - Vector Carryless Multiplication
Let vclmul have 64 bit variant only
Add missing vs1 (rs1) operand for vclmul

Zvkned - NIST Suite: Vector AES Block Cipher
Update test cases to have immediate operands for uimm (*.vi instruction)

Zvknh[ab] - NIST Suite: Vector SHA-2 Secure Hash
Correct vsha2c into vsha2ch and vsha2cl
Fix topic name

Zvksed - ShangMi Suite: SM4 Block Cipher
Fix overloaded name for vsmr4
Fix topic name

Signed-off-by: eop Chen <eop.chen@sifive.com>

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Signed-off-by: eop Chen <eop.chen@sifive.com>

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Signed-off-by: eop Chen <eop.chen@sifive.com>

'vs' instructions will take the first element group from `vs2`, while `vd` can be other settings of register group. This commit adds extra variants for users to choose whatever suits their need. Signed-off-by: eop Chen <eop.chen@sifive.com>

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…s regarding zvl extensions Signed-off-by: eop Chen <eop.chen@sifive.com>

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- Add operand mnemonics for overloaded intrinsics of vaesef/vsaesem/vaesdf/vaesdm - Add vs2 operand for vaeskf2 - Fix vs2 data type for vwsll

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…esef/vsaesem/vaesdf/vaesdm Signed-off-by: eop Chen <eop.chen@sifive.com>

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Signed-off-by: eop Chen <eop.chen@sifive.com>

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…bit-manipulation_used_in_cryptography.md Co-authored-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com> Signed-off-by: Kito Cheng <kito.cheng@gmail.com>

4vtomat · 2024-04-24T16:40:23Z

I'll take over and proceed to work on this patch~

nick-knight requested changes Jun 12, 2023

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auto-generated/vector-crypto/api-testing/vwsll.c Outdated Show resolved Hide resolved

eopXD force-pushed the eopc/vector-crypto branch 4 times, most recently from 2a9812c to 93dcd87 Compare June 28, 2023 10:03

nick-knight requested changes Jul 5, 2023

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topperc reviewed Jul 5, 2023

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auto-generated/vector-crypto/llvm-api-tests/vrol.c Outdated Show resolved Hide resolved