Proposal of the intrinsics for vector crypto

[eopXD]

Update (2023/11/11)

The vector crypto extension is now has a released v1.0.0 [0]. This PR creates intrinsics that exposes interfaces to the vector crypto instructions.

Regarding the data type used in the intrinsics added, this proposal does not model the concept of "element grouping (EGS/EGW)" and reuses the existing data types of the RVV intrinsics (e.g. vuint32m1_t, vuint64m2_t).

The LLVM implementation of the intrinsics is the following: (to be updated to latest v20230531)

• D138810 [RISCV] Support vector crypto extension C intrinsics
• D138809 [RISCV] Support vector crypto extension LLVM IR

[0] https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0

[4vtomat]

I think vs2 of .vs type of this instruction should have lmul1 type.

[eopXD]

Address comments from Craig, Nick, Brandon, and Nicholas. Thank you guys for the review.

Changes:

Zvbb - Vector Bit-manipulation used in Cryptography
Return correct LMUL type for vwsll in the function name suffix
Change rs1 operand to using type size_t

Zvbc - Vector Carryless Multiplication
Let vclmul have 64 bit variant only
Add missing vs1 (rs1) operand for vclmul

Zvkned - NIST Suite: Vector AES Block Cipher
Update test cases to have immediate operands for uimm (*.vi instruction)

Zvknh[ab] - NIST Suite: Vector SHA-2 Secure Hash
Correct vsha2c into vsha2ch and vsha2cl
Fix topic name

Zvksed - ShangMi Suite: SM4 Block Cipher
Fix overloaded name for vsmr4
Fix topic name

[4vtomat]

Rebase