Add workaround for the pcrel issue

As described here by @medusacle: rust-embedded/riscv-rt#25 (comment)
riscv-rust · May 12, 2019 · c24d654 · c24d654
1 parent 85db791
commit c24d654
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/memory-k210.x b/memory-k210.x
@@ -1,7 +1,9 @@
 MEMORY
 {
-    SRAM : ORIGIN = 0x80000000, LENGTH = 6M
-    AI_SRAM : ORIGIN = 0x80600000, LENGTH = 2M
+    /* Workaround for the pcrel issue, as described here:
+       https://github.com/rust-embedded/riscv-rt/issues/25#issuecomment-491518168 */
+    SRAM : ORIGIN = 0xffffffff80000000, LENGTH = 6M
+    AI_SRAM : ORIGIN = 0xffffffff80600000, LENGTH = 2M
     SRAM_NOCACHE : ORIGIN = 0x40000000, LENGTH = 6M
     AI_SRAM_NOCACHE : ORIGIN = 0x40600000, LENGTH = 2M
 }