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Warm reset fix #84

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merged 3 commits into from Mar 7, 2019
Merged

Warm reset fix #84

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130273a
Revert "firmware: Add a barrier instruction for wait for boot hart"
atishp04 Mar 6, 2019
4e44e06
firmware: Add nop to reduce bus traffic.
atishp04 Mar 6, 2019
c24fcb3
firmware: Reset all registers and flush icache
atishp04 Mar 6, 2019
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9 changes: 8 additions & 1 deletion firmware/fw_base.S
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Expand Up @@ -25,6 +25,8 @@ _start:
csrr a6, CSR_MHARTID
blt zero, a6, _wait_for_boot_hart

li ra, 0
call _reset_regs
/* Zero-out BSS */
la a4, _bss_start
la a5, _bss_end
Expand Down Expand Up @@ -114,9 +116,12 @@ _fdt_reloc_done:

/* Wait for boot hart */
_wait_for_boot_hart:
fence rw, rw
la a4, _boot_hart_done
REG_L a5, (a4)
/* Reduce the bus traffic so that boot hart may proceed faster */
nop
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Can you please add a comment inline to describe why this is required?

Also, why can't this be a fence? That seems like a bug somewhere else if a fence doesn't work

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Can you please add a comment inline to describe why this is required?

Done.

Also, why can't this be a fence? That seems like a bug somewhere else if a fence doesn't work

One possible explanation is non-boot cpu cache may have some stale corrupt DTB data which gets written. But this is a just theory and no way to prove it.

That's why commit text says that it's being reverted just for the time being until we figure out the actual reason.

nop
nop
beqz a5, _wait_for_boot_hart

_start_warm:
Expand Down Expand Up @@ -389,6 +394,8 @@ _trap_handler_all_mode:
.globl _reset_regs
_reset_regs:

/* flush the instruction cache */
fence.i
/* Reset all registers except ra, a0,a1 */
li sp, 0
li gp, 0
Expand Down