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This is the code i have return : trying to work with simple vadd, vsub and vrsub with masking register v0.
here is the input data
here is the disassembly file
here is the output:
can any one explain how this masking register works?
Like i have given the inputs as:
1st operand : 2
2nd operand : -1
masking register : 3
From my understanding if the masking register is 3(binary:11), last 2 element result will be calculated and all the other element result will be zero. if the masking register is 4 ( binary : 1111), last 4 element result will be calculated and all other element result will be zero.
The input i have given here is
operand 1 (v4) - 0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000f0000000100000003
operand2 (v8) - 0x000000000000000a000000000000000900000000000000080000000000000007000000000000000600000000000000050000000000000004ffffffffffffffff
masking register(v0) -0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000f0000000000000003
But the output i get here is Add_output(v16)-0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000fffffffff00000001
sub_output(v28)- 0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000f0000000100000003
where the last 2 element having the correct output and remaining element are being copied from the v0 register(masking register)
can anyone tell me whether my understanding is correct or not.
if it is correct, kindly tell me what is the problem exactly that i get a output different(whether i should reinstall my spike ? or whether input format i am giving to the masking register is wrong?)
if my understanding is wrong, kindly explain me how it works.
The text was updated successfully, but these errors were encountered:
This is the code i have return : trying to work with simple vadd, vsub and vrsub with masking register v0.
![image](https://private-user-images.githubusercontent.com/144416964/342353350-2186ebe5-a968-4f62-b1ad-fe158ae7044f.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjE2Nzc0OTcsIm5iZiI6MTcyMTY3NzE5NywicGF0aCI6Ii8xNDQ0MTY5NjQvMzQyMzUzMzUwLTIxODZlYmU1LWE5NjgtNGY2Mi1iMWFkLWZlMTU4YWU3MDQ0Zi5wbmc_WC1BbXotQWxnb3JpdGhtPUFXUzQtSE1BQy1TSEEyNTYmWC1BbXotQ3JlZGVudGlhbD1BS0lBVkNPRFlMU0E1M1BRSzRaQSUyRjIwMjQwNzIyJTJGdXMtZWFzdC0xJTJGczMlMkZhd3M0X3JlcXVlc3QmWC1BbXotRGF0ZT0yMDI0MDcyMlQxOTM5NTdaJlgtQW16LUV4cGlyZXM9MzAwJlgtQW16LVNpZ25hdHVyZT02MzQ3ODMwYjI0MTdlM2MxYjg0YWI0YWE4YzY4YTMxYzFkNWUyODg0NmY3Mzg1YTJiYTBkN2FmYjZkYmM2MGM0JlgtQW16LVNpZ25lZEhlYWRlcnM9aG9zdCZhY3Rvcl9pZD0wJmtleV9pZD0wJnJlcG9faWQ9MCJ9.c41r5fTvOvuZwxJNfjEU8wAeXmVyJZbcNZFk5n3KU14)
here is the input data
![image](https://private-user-images.githubusercontent.com/144416964/342353760-9b259a36-7c86-456c-b63c-0d612c559586.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjE2Nzc0OTcsIm5iZiI6MTcyMTY3NzE5NywicGF0aCI6Ii8xNDQ0MTY5NjQvMzQyMzUzNzYwLTliMjU5YTM2LTdjODYtNDU2Yy1iNjNjLTBkNjEyYzU1OTU4Ni5wbmc_WC1BbXotQWxnb3JpdGhtPUFXUzQtSE1BQy1TSEEyNTYmWC1BbXotQ3JlZGVudGlhbD1BS0lBVkNPRFlMU0E1M1BRSzRaQSUyRjIwMjQwNzIyJTJGdXMtZWFzdC0xJTJGczMlMkZhd3M0X3JlcXVlc3QmWC1BbXotRGF0ZT0yMDI0MDcyMlQxOTM5NTdaJlgtQW16LUV4cGlyZXM9MzAwJlgtQW16LVNpZ25hdHVyZT02NmU4MTMyMjg5NDBkYTM2YmUwMzJkZjE2OWRhMGUwYmZhMWE0MzY1MjliMTliMWRkMzZlZWJlMmNiM2FmNTNlJlgtQW16LVNpZ25lZEhlYWRlcnM9aG9zdCZhY3Rvcl9pZD0wJmtleV9pZD0wJnJlcG9faWQ9MCJ9.3Uv2N0Wsnb4AoYOHgKK3LKQ2PIliNgsh-AZoNJIXBHw)
here is the disassembly file
![image](https://private-user-images.githubusercontent.com/144416964/342355514-b2969341-9ae2-4de7-b02f-ed2fbc0265ee.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjE2Nzc0OTcsIm5iZiI6MTcyMTY3NzE5NywicGF0aCI6Ii8xNDQ0MTY5NjQvMzQyMzU1NTE0LWIyOTY5MzQxLTlhZTItNGRlNy1iMDJmLWVkMmZiYzAyNjVlZS5wbmc_WC1BbXotQWxnb3JpdGhtPUFXUzQtSE1BQy1TSEEyNTYmWC1BbXotQ3JlZGVudGlhbD1BS0lBVkNPRFlMU0E1M1BRSzRaQSUyRjIwMjQwNzIyJTJGdXMtZWFzdC0xJTJGczMlMkZhd3M0X3JlcXVlc3QmWC1BbXotRGF0ZT0yMDI0MDcyMlQxOTM5NTdaJlgtQW16LUV4cGlyZXM9MzAwJlgtQW16LVNpZ25hdHVyZT02ZjcwZGIwNGJmZTc2NDdiOTBkYTIwYWYwZTFkMjI2NGUwYjgyYjYwOTJmZDcyNWY3NGI0ODg1ODk1NDE2MjJhJlgtQW16LVNpZ25lZEhlYWRlcnM9aG9zdCZhY3Rvcl9pZD0wJmtleV9pZD0wJnJlcG9faWQ9MCJ9.7ADs5lNGfNVORIZjrXIWS9R1N9Ftc0I1qQfe2OTpP84)
here is the output:
![image](https://private-user-images.githubusercontent.com/144416964/342356293-28babd55-df45-45b0-822b-5e789fc9fd41.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjE2Nzc0OTcsIm5iZiI6MTcyMTY3NzE5NywicGF0aCI6Ii8xNDQ0MTY5NjQvMzQyMzU2MjkzLTI4YmFiZDU1LWRmNDUtNDViMC04MjJiLTVlNzg5ZmM5ZmQ0MS5wbmc_WC1BbXotQWxnb3JpdGhtPUFXUzQtSE1BQy1TSEEyNTYmWC1BbXotQ3JlZGVudGlhbD1BS0lBVkNPRFlMU0E1M1BRSzRaQSUyRjIwMjQwNzIyJTJGdXMtZWFzdC0xJTJGczMlMkZhd3M0X3JlcXVlc3QmWC1BbXotRGF0ZT0yMDI0MDcyMlQxOTM5NTdaJlgtQW16LUV4cGlyZXM9MzAwJlgtQW16LVNpZ25hdHVyZT1lZWMyNDQwMzA3ZmNlN2MzNTZhNjg1YTdjOTIxYmQzZjE3NDA4MmU1ZjU4ZGMwYTU0ODIzMDYzNjYzZjAxYzJkJlgtQW16LVNpZ25lZEhlYWRlcnM9aG9zdCZhY3Rvcl9pZD0wJmtleV9pZD0wJnJlcG9faWQ9MCJ9.5CQRkZbsnNnQIxzr4edyVKWcjX20ZwlSzoDJJxC17ms)
can any one explain how this masking register works?
Like i have given the inputs as:
1st operand : 2
2nd operand : -1
masking register : 3
From my understanding if the masking register is 3(binary:11), last 2 element result will be calculated and all the other element result will be zero. if the masking register is 4 ( binary : 1111), last 4 element result will be calculated and all other element result will be zero.
The input i have given here is
operand 1 (v4) - 0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000f0000000100000003
operand2 (v8) - 0x000000000000000a000000000000000900000000000000080000000000000007000000000000000600000000000000050000000000000004ffffffffffffffff
masking register(v0) -0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000f0000000000000003
The expected output from my understanding:
Add_output (v16)- 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffff00000001
sub_output (v28)- 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000003
But the output i get here is Add_output(v16)-0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000fffffffff00000001
sub_output(v28)- 0x00000000000000000000000000000000000000000000000a000000000000000900000000000000080000000000000007000000000000000f0000000100000003
where the last 2 element having the correct output and remaining element are being copied from the v0 register(masking register)
can anyone tell me whether my understanding is correct or not.
if it is correct, kindly tell me what is the problem exactly that i get a output different(whether i should reinstall my spike ? or whether input format i am giving to the masking register is wrong?)
if my understanding is wrong, kindly explain me how it works.
The text was updated successfully, but these errors were encountered: