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prefetch.w.adoc

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prefetch.w

Synopsis

Provide a HINT to hardware that the cache block containing the effective address is likely to be accessed by a data write in the near future

Mnemonic

prefetch.w offset(base)

Encoding
{reg:[
	{ bits: 7,  name: 0x13,        attr: ['OP-IMM'] },
	{ bits: 5,  name: 0x0,         attr: ['offset[4:0]'] },
	{ bits: 3,  name: 0x6,         attr: ['ORI'] },
	{ bits: 5,  name: 'rs1',       attr: ['base'] },
	{ bits: 5,  name: 0x3,         attr: ['PREFETCH.W'] },
	{ bits: 7, name: 'imm[11:5]',  attr: ['offset[11:5]'] },
]}
Description

A prefetch.w instruction indicates to hardware that the cache block containing the effective address is likely to be accessed by a data write (i.e. store) in the near future.

An implementation may opt to cache a copy of the cache block in a cache accessed by a data write in order to improve memory access latency, but this behavior is not required.

Operation
TODO