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target:riscv: optimize register accesses #842
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I love this. Unnecessary register accesses annoy me every time I look at a log and I just haven't gotten around to fixing them.
I haven't done a proper review yet.
Can you add short comments to each register function that highlights the difference between all of them?
I am not sure if using 'gdb_regno' in low-level debug access functions is appropriate. |
I also think this is a valid point of concern. However, the transition from
In such uses it is silently expected that
So, in my opinion, the creation of such an enumeration and conversion should be done in a separate commit and is somewhat out of scope of this PR. |
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Addressed. |
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Can you make sure to run make all
in riscv-tests/debug? That has coverage for at least some of the scratch RAM cases.
This is a large change, and I haven't entirely grokked it. Can you give an example or two of cases where registers are now cached that they wouldn't be previously?
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These changes look really fine 👍
Thank you for taking the time to improve the code.
I have only smaller suggestions.
To sum up, after the change:
|
Is is definitely and always the case that there are no registers that cause side effects when the value already stored is written again and, for which, ignoring such writes will result in incorrect behaviour? |
I've run all the tests from |
This question interests me as well. My understanding is that there isn't one, but I'm not sure. |
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Thanks for showing the difference in vector accesses. That's a very nice improvement.
Last I really looked, spike-multi passed for me but it was hugely slower than it used to be. I'm not sure what happened, and I've been ignoring the problem. They're really just to test connecting OpenOCD RV32 and RV64 targets. I don't think your code would have been affected by that. |
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@en-sc Thank you for addressing the review feedback so far.
I have visually re-checked the merge request once again and it looks fine. In summary, I have only:
- Few minor suggestions about comments & code style.
- One doubt about the save & restore of target state in
examine()
. I think this part had been reworked in a better way already, but now this save & restore is back. Why? :)
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I've done one last visual check of the changes and it looks good to me. Thanks.
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@en-sc Also please make sure your branch is rebased on top of current |
Since writing a register can make some GPRs dirty (e.g. S0, S1), registers should be flushed in reverse order, so GPRs are flushed last. Change-Id: Ice352a4df4ae064619c0f9905db634a7b57e4711 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: Ia476251e835fa5fd129ae6b679c6049c5c60c716 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit introduces a new function, which can be used to reduce number of register accesses. Change-Id: I125809726eb7797b11121175c3ad66bedb66dd0d Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Introduce riscv_write_register to prep_for_register/vector_access and cleanup_after_register/vector_access. Change-Id: I77a0a06ac6f12eceec309f0aff94aa77bd56ff55 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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Done. |
Change-Id: I45731d501f6261c4142c70afacf3fbbe42cf2806 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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Last change was a bugfix. Current version passes tests from |
@timsifive, can this PR be merged today, or do I need to do something? |
I'm giving @JanMatCodasip a final chance at commenting, but otherwise I was going to merge it tomorrow. |
🎆 |
These commits reduce the number of accesses to target's registers by better utilizing register cache.