RISC-V: Fix disassemble for c.li, c.andi and c.addiw

ChangeLog 2017-05-03 Kito Cheng <kito.cheng@gmail.com> * riscv-dis.c (print_insn_args): Handle 'Co' operands.
riscvarchive · May 5, 2017 · 3f21b5c · 3f21b5c
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diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
+
+	* riscv-dis.c (print_insn_args): Handle 'Co' operands.
+
 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 
 	* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	    case 'i':
 	      print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
 	      break;
+	    case 'o':
 	    case 'j':
 	      print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
 	      break;