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fix problems in the review
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@pz9115
pz9115 committed Apr 14, 2021
1 parent 72ef429 commit a69bb36
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Showing 6 changed files with 97 additions and 172 deletions.
16 changes: 3 additions & 13 deletions bfd/elfxx-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1161,15 +1161,7 @@ riscv_ext_dont_care_version (const char *subset)
if (strcmp (subset, "g") == 0
|| strcmp (subset, "k") == 0
|| strcmp (subset, "zicsr") == 0
|| strcmp (subset, "zifencei") == 0
|| strcmp (subset, "zkg") == 0
|| strcmp (subset, "zkb") == 0
|| strcmp (subset, "zkr") == 0
|| strcmp (subset, "zkne") == 0
|| strcmp (subset, "zknd") == 0
|| strcmp (subset, "zknh") == 0
|| strcmp (subset, "zksed") == 0
|| strcmp (subset, "zksh") == 0)
|| strcmp (subset, "zifencei") == 0)
return TRUE;
return FALSE;
}
Expand Down Expand Up @@ -1607,7 +1599,8 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,

static const char * const riscv_std_z_ext_strtab[] =
{
"zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", "zkb", "zkg", "zkne", "zknd", "zknh", "zkr", "zksed", "zksh", NULL
"zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", "zkb", "zkg",
"zkn", "zkne", "zknd", "zknh", "zkr", "zks", "zksed", "zksh", NULL
};

static const char * const riscv_std_s_ext_strtab[] =
Expand Down Expand Up @@ -1795,9 +1788,6 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
riscv_parse_add_subset (rps, "zksh",
RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, TRUE);
riscv_parse_add_subset (rps, "zknh",
RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, TRUE);
}
else if ((riscv_lookup_subset (rps->subset_list, "zkn", &subset)))
{
Expand Down
55 changes: 32 additions & 23 deletions gas/config/tc-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -143,6 +143,18 @@ static const struct riscv_ext_version ext_version_table[] =
{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},

{"zkg", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zkb", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zkr", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zkn", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zkne", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zknd", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zknh", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zks", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zksed", ISA_SPEC_CLASS_DRAFT, 0, 90},
{"zksh", ISA_SPEC_CLASS_DRAFT, 0, 90},


/* Terminate the list. */
{NULL, 0, 0, 0}
};
Expand Down Expand Up @@ -340,9 +352,6 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
return riscv_subset_supports ("zba");
case INSN_CLASS_ZBC:
return riscv_subset_supports ("zbc");
case INSN_CLASS_ZBA_OR_ZBB:
return (riscv_subset_supports ("zba")
|| riscv_subset_supports ("zbb"));

case INSN_CLASS_ZKG:
return riscv_subset_supports ("zkg");
Expand Down Expand Up @@ -1097,8 +1106,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'I': break; /* Macro operand, must be constant. */
case 'D': /* RD, floating point. */
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
case 'Y': USE_BITS (OP_MASK_RCON, OP_SH_RCON); break;
case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
case 'Y': USE_BITS (OP_MASK_RCON, OP_SH_RCON); break;
case 'Z': /* RS1, CSR number. */
case 'S': /* RS1, floating point. */
case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
Expand Down Expand Up @@ -2726,26 +2735,26 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
break;

case 'y': /* bs immediate */
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
if ((unsigned long)imm_expr->X_add_number > 3)
as_bad(_("Improper bs immediate (%lu)"),
(unsigned long) imm_expr->X_add_number);
INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
if ((unsigned long)imm_expr->X_add_number > 3)
as_bad(_("Improper bs immediate (%lu)"),
(unsigned long) imm_expr->X_add_number);
INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;

case 'Y': /* rcon immediate */
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
if ((unsigned long)imm_expr->X_add_number > 10)
as_bad(_("Improper rcon immediate (%lu)"),
(unsigned long) imm_expr->X_add_number);
INSERT_OPERAND(RCON, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
if ((unsigned long)imm_expr->X_add_number > 10)
as_bad(_("Improper rcon immediate (%lu)"),
(unsigned long) imm_expr->X_add_number);
INSERT_OPERAND(RCON, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;

case 'z':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
Expand Down
72 changes: 0 additions & 72 deletions include/opcode/riscv-opc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -621,54 +621,6 @@
#define MASK_C_LDSP 0xe003
#define MATCH_C_SDSP 0xe002
#define MASK_C_SDSP 0xe003
#define MATCH_CUSTOM0 0xb
#define MASK_CUSTOM0 0x707f
#define MATCH_CUSTOM0_RS1 0x200b
#define MASK_CUSTOM0_RS1 0x707f
#define MATCH_CUSTOM0_RS1_RS2 0x300b
#define MASK_CUSTOM0_RS1_RS2 0x707f
#define MATCH_CUSTOM0_RD 0x400b
#define MASK_CUSTOM0_RD 0x707f
#define MATCH_CUSTOM0_RD_RS1 0x600b
#define MASK_CUSTOM0_RD_RS1 0x707f
#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
#define MATCH_CUSTOM1 0x2b
#define MASK_CUSTOM1 0x707f
#define MATCH_CUSTOM1_RS1 0x202b
#define MASK_CUSTOM1_RS1 0x707f
#define MATCH_CUSTOM1_RS1_RS2 0x302b
#define MASK_CUSTOM1_RS1_RS2 0x707f
#define MATCH_CUSTOM1_RD 0x402b
#define MASK_CUSTOM1_RD 0x707f
#define MATCH_CUSTOM1_RD_RS1 0x602b
#define MASK_CUSTOM1_RD_RS1 0x707f
#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
#define MATCH_CUSTOM2 0x5b
#define MASK_CUSTOM2 0x707f
#define MATCH_CUSTOM2_RS1 0x205b
#define MASK_CUSTOM2_RS1 0x707f
#define MATCH_CUSTOM2_RS1_RS2 0x305b
#define MASK_CUSTOM2_RS1_RS2 0x707f
#define MATCH_CUSTOM2_RD 0x405b
#define MASK_CUSTOM2_RD 0x707f
#define MATCH_CUSTOM2_RD_RS1 0x605b
#define MASK_CUSTOM2_RD_RS1 0x707f
#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
#define MATCH_CUSTOM3 0x7b
#define MASK_CUSTOM3 0x707f
#define MATCH_CUSTOM3_RS1 0x207b
#define MASK_CUSTOM3_RS1 0x707f
#define MATCH_CUSTOM3_RS1_RS2 0x307b
#define MASK_CUSTOM3_RS1_RS2 0x707f
#define MATCH_CUSTOM3_RD 0x407b
#define MASK_CUSTOM3_RD 0x707f
#define MATCH_CUSTOM3_RD_RS1 0x607b
#define MASK_CUSTOM3_RD_RS1 0x707f
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
#define MASK_CUSTOM3_RD_RS1_RS2 0x707f

/* K-ext*/
#define MATCH_POLLENTROPY 0xf1502073
Expand Down Expand Up @@ -1309,30 +1261,6 @@ DECLARE_INSN(aes64esm,MATCH_AES64ESM,MASK_AES64ESM)
DECLARE_INSN(aes64es,MATCH_AES64ES,MASK_AES64ES)
DECLARE_INSN(aes64dsm,MATCH_AES64DSM,MASK_AES64DSM)
DECLARE_INSN(aes64ds,MATCH_AES64DS,MASK_AES64DS)
DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
#endif /* DECLARE_INSN. */

#ifdef DECLARE_CSR
Expand Down
59 changes: 29 additions & 30 deletions include/opcode/riscv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -308,36 +308,35 @@ static const char * const riscv_pred_succ[16] =

/* All RISC-V instructions belong to at least one of these classes. */
enum riscv_insn_class
{
INSN_CLASS_NONE,

INSN_CLASS_I,
INSN_CLASS_C,
INSN_CLASS_A,
INSN_CLASS_M,
INSN_CLASS_F,
INSN_CLASS_D,
INSN_CLASS_Q,
INSN_CLASS_F_AND_C,
INSN_CLASS_D_AND_C,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
INSN_CLASS_ZBA_OR_ZBB,
INSN_CLASS_ZKG,
INSN_CLASS_ZKB,
INSN_CLASS_ZKR,
INSN_CLASS_ZKNE,
INSN_CLASS_ZKND,
INSN_CLASS_ZKNH,
INSN_CLASS_ZKNE_OR_ZKND_OR_ZKNH_OR_ZKG_OR_ZKB,
INSN_CLASS_ZKSED,
INSN_CLASS_ZKSH,
INSN_CLASS_ZKSED_OR_ZKSH_OR_ZKG_OR_ZKB,
};
{
INSN_CLASS_NONE,

INSN_CLASS_I,
INSN_CLASS_C,
INSN_CLASS_A,
INSN_CLASS_M,
INSN_CLASS_F,
INSN_CLASS_D,
INSN_CLASS_Q,
INSN_CLASS_F_AND_C,
INSN_CLASS_D_AND_C,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
INSN_CLASS_ZKG,
INSN_CLASS_ZKB,
INSN_CLASS_ZKR,
INSN_CLASS_ZKNE,
INSN_CLASS_ZKND,
INSN_CLASS_ZKNH,
INSN_CLASS_ZKNE_OR_ZKND_OR_ZKNH_OR_ZKG_OR_ZKB,
INSN_CLASS_ZKSED,
INSN_CLASS_ZKSH,
INSN_CLASS_ZKSED_OR_ZKSH_OR_ZKG_OR_ZKB,
};

/* This structure holds information for a particular instruction. */
struct riscv_opcode
Expand Down
1 change: 0 additions & 1 deletion opcodes/riscv-dis.c
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Original file line number Diff line number Diff line change
Expand Up @@ -415,7 +415,6 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RCON, l));
break;


case 'Z':
print (info->stream, "%d", rs1);
break;
Expand Down
66 changes: 33 additions & 33 deletions opcodes/riscv-opc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -750,39 +750,6 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },

/*Scalar Krypoto instructions. */
{"pollentropy", 0, INSN_CLASS_ZKR, "d", MATCH_POLLENTROPY, MASK_POLLENTROPY, match_opcode, INSN_ALIAS },
{"getnoise", 0, INSN_CLASS_ZKR, "d", MATCH_GETNOISE, MASK_GETNOISE, match_opcode, INSN_ALIAS },
{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
{"sm4ed", 0, INSN_CLASS_ZKSED, "s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
{"sm4ks", 0, INSN_CLASS_ZKSED, "s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
{"aes32esmi", 32, INSN_CLASS_ZKNE, "s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
{"aes32esi", 32, INSN_CLASS_ZKNE, "s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
{"aes32dsmi", 32, INSN_CLASS_ZKND, "s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
{"aes32dsi", 32, INSN_CLASS_ZKND, "s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
{"aes64ks1i", 64, INSN_CLASS_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
{"aes64ks2", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },

/* Supervisor instructions */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS },
{"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
Expand Down Expand Up @@ -815,6 +782,39 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },

/*Scalar Krypoto instructions. */
{"pollentropy", 0, INSN_CLASS_ZKR, "d", MATCH_POLLENTROPY, MASK_POLLENTROPY, match_opcode, INSN_ALIAS },
{"getnoise", 0, INSN_CLASS_ZKR, "d", MATCH_GETNOISE, MASK_GETNOISE, match_opcode, INSN_ALIAS },
{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
{"sm4ed", 0, INSN_CLASS_ZKSED, "s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
{"sm4ks", 0, INSN_CLASS_ZKSED, "s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
{"aes32esmi", 32, INSN_CLASS_ZKNE, "s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
{"aes32esi", 32, INSN_CLASS_ZKNE, "s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
{"aes32dsmi", 32, INSN_CLASS_ZKND, "s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
{"aes32dsi", 32, INSN_CLASS_ZKND, "s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
{"aes64ks1i", 64, INSN_CLASS_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
{"aes64ks2", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },

/* RVB instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
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