Use RISCV_PTR, not PTR

riscvarchive · May 24, 2017 · 73b7155 · 73b7155
1 parent 874fc48
commit 73b7155
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Showing 5 changed files with 50 additions and 38 deletions.
diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
@@ -35,17 +35,29 @@
 #define LGREG		__REG_SEL(3, 2)
 
 #if __SIZEOF_POINTER__ == 8
-#define __PTR_SEL(a, b)	__ASM_STR(a)
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
+#define RISCV_LGPTR		4
+#else
+#define RISCV_PTR		".word"
+#define RISCV_SZPTR		"4"
+#define RISCV_LGPTR		"2"
+#endif
 #elif __SIZEOF_POINTER__ == 4
-#define __PTR_SEL(a, b)	__ASM_STR(b)
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.word
+#define RISCV_SZPTR		4
+#define RISCV_LGPTR		2
+#else
+#define RISCV_PTR		".word"
+#define RISCV_SZPTR		"4"
+#define RISCV_LGPTR		"2"
+#endif
 #else
 #error "Unexpected __SIZEOF_POINTER__"
 #endif
 
-#define PTR		__PTR_SEL(.dword, .word)
-#define SZPTR		__PTR_SEL(8, 4)
-#define LGPTR		__PTR_SEL(3, 2)
-
 #if (__SIZEOF_INT__ == 4)
 #define INT		__ASM_STR(.word)
 #define SZINT		__ASM_STR(4)

diff --git a/arch/riscv/include/asm/bug.h b/arch/riscv/include/asm/bug.h
@@ -31,8 +31,8 @@ typedef u32 bug_insn_t;
 #define __BUG_ENTRY_ADDR	INT " 1b - 2b"
 #define __BUG_ENTRY_FILE	INT " %0 - 2b"
 #else
-#define __BUG_ENTRY_ADDR	PTR " 1b"
-#define __BUG_ENTRY_FILE	PTR " %0"
+#define __BUG_ENTRY_ADDR	RISCV_PTR " 1b"
+#define __BUG_ENTRY_FILE	RISCV_PTR " %0"
 #endif
 
 #ifdef CONFIG_DEBUG_BUGVERBOSE

diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h
@@ -148,8 +148,8 @@ do {								\
 		"	jump 2b, %2\n"				\
 		"	.previous\n"				\
 		"	.section __ex_table,\"a\"\n"		\
-		"	.balign " SZPTR "\n"			\
-		"	" PTR " 1b, 3b\n"			\
+		"	.balign " RISCV_SZPTR "\n"			\
+		"	" RISCV_PTR " 1b, 3b\n"			\
 		"	.previous"				\
 		: "+r" (err), "=&r" (x), "=r" (__tmp)		\
 		: "m" (*(ptr)), "i" (-EFAULT));			\
@@ -190,9 +190,9 @@ do {								\
 		"	jump 3b, %3\n"				\
 		"	.previous\n"				\
 		"	.section __ex_table,\"a\"\n"		\
-		"	.balign " SZPTR "\n"			\
-		"	" PTR " 1b, 4b\n"			\
-		"	" PTR " 2b, 4b\n"			\
+		"	.balign " RISCV_SZPTR "\n"			\
+		"	" RISCV_PTR " 1b, 4b\n"			\
+		"	" RISCV_PTR " 2b, 4b\n"			\
 		"	.previous"				\
 		: "+r" (err), "=&r" (__lo), "=r" (__hi),	\
 			"=r" (__tmp)				\
@@ -297,8 +297,8 @@ do {								\
 		"	jump 2b, %1\n"				\
 		"	.previous\n"				\
 		"	.section __ex_table,\"a\"\n"		\
-		"	.balign " SZPTR "\n"			\
-		"	" PTR " 1b, 3b\n"			\
+		"	.balign " RISCV_SZPTR "\n"			\
+		"	" RISCV_PTR " 1b, 3b\n"			\
 		"	.previous"				\
 		: "+r" (err), "=r" (__tmp), "=m" (*(ptr))	\
 		: "rJ" (__x), "i" (-EFAULT));			\
@@ -337,9 +337,9 @@ do {								\
 		"	jump 2b, %1\n"				\
 		"	.previous\n"				\
 		"	.section __ex_table,\"a\"\n"		\
-		"	.balign " SZPTR "\n"			\
-		"	" PTR " 1b, 4b\n"			\
-		"	" PTR " 2b, 4b\n"			\
+		"	.balign " RISCV_SZPTR "\n"			\
+		"	" RISCV_PTR " 1b, 4b\n"			\
+		"	" RISCV_PTR " 2b, 4b\n"			\
 		"	.previous"				\
 		: "+r" (err), "=r" (__tmp),			\
 			"=m" (__ptr[__LSW]),			\

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
@@ -154,7 +154,7 @@ ENTRY(handle_exception)
 	beq s4, t0, handle_syscall
 
 	/* Handle other exceptions */
-	slli t0, s4, LGPTR
+	slli t0, s4, RISCV_LGPTR
 	la t1, excp_vect_table
 	la t2, excp_vect_table_end
 	move a0, sp /* pt_regs */
@@ -184,7 +184,7 @@ check_syscall_nr:
 	/* Syscall number held in a7 */
 	bgeu a7, t0, 1f
 	la s0, sys_call_table
-	slli t0, a7, LGPTR
+	slli t0, a7, RISCV_LGPTR
 	add s0, s0, t0
 	REG_L s0, 0(s0)
 1:
@@ -400,22 +400,22 @@ ENDPROC(__fstate_restore)
 	.section ".rodata"
 	/* Exception vector table */
 ENTRY(excp_vect_table)
-	PTR do_trap_insn_misaligned
-	PTR do_trap_unknown /* instruction access exception */
-	PTR do_trap_insn_illegal
-	PTR do_trap_break
-	PTR do_trap_unknown
-	PTR do_trap_unknown /* load access exception */
-	PTR do_trap_amo_misaligned
-	PTR do_trap_unknown /* store access exception */
-	PTR do_trap_unknown /* handle_syscall */
-	PTR do_trap_unknown
-	PTR do_trap_unknown
-	PTR do_trap_unknown
-	PTR do_page_fault   /* instruction page fault */
-	PTR do_page_fault   /* load page fault */
-	PTR do_trap_unknown
-	PTR do_page_fault   /* store page fault */
+	RISCV_PTR do_trap_insn_misaligned
+	RISCV_PTR do_trap_unknown /* instruction access exception */
+	RISCV_PTR do_trap_insn_illegal
+	RISCV_PTR do_trap_break
+	RISCV_PTR do_trap_unknown
+	RISCV_PTR do_trap_unknown /* load access exception */
+	RISCV_PTR do_trap_amo_misaligned
+	RISCV_PTR do_trap_unknown /* store access exception */
+	RISCV_PTR do_trap_unknown /* handle_syscall */
+	RISCV_PTR do_trap_unknown
+	RISCV_PTR do_trap_unknown
+	RISCV_PTR do_trap_unknown
+	RISCV_PTR do_page_fault   /* instruction page fault */
+	RISCV_PTR do_page_fault   /* load page fault */
+	RISCV_PTR do_trap_unknown
+	RISCV_PTR do_page_fault   /* store page fault */
 excp_vect_table_end:
 END(excp_vect_table)
 
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
@@ -8,8 +8,8 @@
 _epc:
 	\op \reg, \addr
 	.section __ex_table,"a"
-	.balign SZPTR
-	PTR _epc, \lbl
+	.balign RISCV_SZPTR
+	RISCV_PTR _epc, \lbl
 	.previous
 	.endm