Updating with assigned bit positions

Signed-off-by: ved-rivos <91900059+ved-rivos@users.noreply.github.com>

svadu.adoc

@@ -54,16 +54,16 @@ translation process is as follows:
     a store, also set `pte.d` to 1.
 ... If the comparison fails, return to step 2
 
-The Svadu extension adds the `HADE` bit to `menvcfg`. When `menvcfg.HADE` is 1,
-hardware updating of PTE A/D bits is enabled during single-stage address
-translation. When the hypervisor extension is implemented, if `menvcfg.HADE` is
-1, hardware updating of PTE A/D bits is enabled during G-stage address
-translation.  When `menvcfg.HADE` is zero, the implementation behaves as though
-Svadu is not implemented. If Svadu is not implemented, `menvcfg.HADE` is
-read-only zero. Furthermore, for implementations with the hypervisor extension,
-`henvcfg.HADE` is read-only zero if `menvcfg.HADE` is zero.
+The Svadu extension adds the `HADE` bit (bit 61) to `menvcfg`. When 
+`menvcfg.HADE` is 1, hardware updating of PTE A/D bits is enabled during
+single-stage address translation. When the hypervisor extension is implemented,
+if `menvcfg.HADE` is 1, hardware updating of PTE A/D bits is enabled during
+G-stage address translation.  When `menvcfg.HADE` is zero, the implementation
+behaves as though Svadu is not implemented. If Svadu is not implemented, 
+`menvcfg.HADE` is read-only zero. Furthermore, for implementations with the
+hypervisor extension, `henvcfg.HADE` is read-only zero if `menvcfg.HADE` is zero.
 
 When the hypervisor extension is implemented, the Svadu extension adds the
-`HADE` bit to `henvcfg`. When `henvcfg.HADE` is 1, hardware updating of PTE A/D
-bits is enabled during VS-stage address translation. When `henvcfg.HADE` is
-zero, the implementation behaves as though Svadu is not implemented.
+`HADE` bit (bit 61) to `henvcfg`. When `henvcfg.HADE` is 1, hardware updating of
+PTE A/D bits is enabled during VS-stage address translation. When `henvcfg.HADE`
+is zero, the implementation behaves as though Svadu is not implemented.