MIPS capstone problems

[XVilka]

Once most MIPS RzIL uplifting is implemented, we should think about precision. As the MIPS plugin is based on capstone, we have these:

• padduw not implemented on MIPS capstone-engine/capstone#940
• Unknow opcodes for MIPS32 BE capstone-engine/capstone#1054
• MIPS32R6: "pref" and "cache" missing operand unless preceeded by instruction capstone-engine/capstone#1133
• error in MIPS big endian assembly, instruction is '00c0502d' capstone-engine/capstone#1267
• MIPS Coprocessor 0 register naming capstone-engine/capstone#1508
• MIPS regs_access unsupported capstone-engine/capstone#1519
• MIPS: Too much reliance on move instructions capstone-engine/capstone#1613
• MIPS: disassemble instruction c.ule.d incorrectly capstone-engine/capstone#1634
• MIPS: mistake in disassembling special privileged instruction (MFC) capstone-engine/capstone#1673
• MIPS CS_GRP_CALL and CS_GRP_RET broken for simple case capstone-engine/capstone#1680
• Inconsistent behavior of Mips_option() and other XX_option() capstone-engine/capstone#1743
• MIPS: add/fix support for "rdhwr" instruction  capstone-engine/capstone#1780
• MIPS partial support for c.eq.d and friends capstone-engine/capstone#1851
• 'regs_access()' is still not supported in MIPS capstone-engine/capstone#1869
• For the problem of JIALC instruction parsing on MIPS 32 capstone-engine/capstone#1957
• MIPS lacks CS_OPT_SYNTAX_NOREGNAME support capstone-engine/capstone#1958
• Wrong disassembly in MIPS32  capstone-engine/capstone#1990

cc @junchao-loongson