LLVM replaces Manual

[Rot127]

Hi,

so this is basically a complete rewrite of the generation code. I used LLVM as the source of information and no longer the Programmers Reference Manual. The reason is mainly that the parsing had to be done for each Manual again. This was error prone and could not be tested easily (and there are a lot more reasons).

There are still some non functional things missing in this version (list below), but I won't have that much time in the next two weeks to work on it further, so I just wanted to put it out for you to review.

I am very happy about any remarks, requests or improvement ideas!

Also I really hope the code is easy to understand, maintainable and extendable. If you have any remarks in this regard, please let me know as well!

Features comparison

Old	New	Notes
v5 - v62 instr set	LLVM instr. set (v5-v68 + HVX)	n-o-o-n added not public instruction to its plugin. We do not have those.
Incorrect sub register parsing	Has been fixed
Only GPRs in register profile	All registers in register profile + argument and return register
Hard coded calling convention (arg regs/return regs)	CC derived from LLVM	CC for HVX is not added yet. Rizin can not handle more than 10 arg registers.
Hard to update (needs parsing code for each Manual ver.)	Easy to update (as long as LLVM does not change too much.)
Does not distinguish between different Hexagon versions.	same	This could be problematic because after v66 vector registers were 1024bit wide instead of 512bit. This plugin sets the sizeof vector registers to 1024bit.
No difference between 32bit immediate values and non 32bit values in the syntax.	32bit prefixed with ##. Non 32bit with #
Neg. immediate values printed as unsigned int	Signed immediate values!	##0xffffffff -> ##-0x1 - My favorite :D
None	Hardware loop support
None	Instr. packet highlighting

TODO

• HVX register (vector registers) have no special type in the register protocol yet. They are treated as GPRs at the moment. See: Add vector and control register type rizin#1287
• Double registers are listed as independent registers in the register profile. This should be changed.
• Some asm tests fail on purpose (because of the previous points).
• Rizin analysis tests missing -> Tested only by manually checking it in rizin (which works fine).
• No UTF-8 free assembly code at the moment (Instr. packets are prefixed with Unicode chars). -> UTF-8 chars are removed.
• Missing Control double registers (C21:20 - C29:28) encodings. This is a problem in the LLVM source. Probably have to create a pull request there.
• HVX instructions and register types are not tested yet (didn't get the IDE to compile HVX code in a reasonable time).
• For consistency: All not generated files should be placed in handwritten and then moved.
• Set all rizin instruction types for suitable instructions in hexagon_analyses.c. Not just jmp instructions.
• Adapt syntax highlighting.
• The method for parsing a Duplex and normal instruction are almost the same. This needs some refactoring.
• (some more tiny things. See comments in code.)

[XVilka]

Overall it's a very good approach, I like it. Will check more thoroughly soon

[XVilka]

Please add SPDX with license and your copyright as well.

[XVilka]

Three more things:

• Please check with reuse lint if all files are SPDX-ed properly
• For files that aren't sources, you can use .reuse/dep5 as in Rizin https://github.com/rizinorg/rizin/blob/dev/.reuse/dep5
• Please copy .clang-format from Rizin repo and check if C files are formatted properly https://github.com/rizinorg/rizin/blob/dev/.clang-format

[XVilka]

It's good enough. But having able to operate without UTF-8 is crucial before merging and synchronizing it in Rizin.

[Rot127]

Just recognized that two tests fail and I do not know why, yet. Will make another push today or maybe next week. Thank you for the feedback so far! Jul 16, 2021 07:50:04 Anton Kochkov ***@***.***>:

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***@***.**** approved this pull request. It's good enough. But having able to operate without UTF-8 is crucial before merging and synchronizing it in Rizin. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub[#4 (review)], or unsubscribe[https://github.com/notifications/unsubscribe-auth/AK5ET6EH3PUNP2XW2TC2S73TX7CAVANCNFSM5AEE4Y4A]. [data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAADUAAAA1CAYAAADh5qNwAAAAAXNSR0IArs4c6QAAAARzQklUCAgICHwIZIgAAAAiSURBVGiB7cEBDQAAAMKg909tDjegAAAAAAAAAAAAAIB7AywZAAGURgP6AAAAAElFTkSuQmCC###24x24:true###][Tracking image][https://github.com/notifications/beacon/AK5ET6EY6F7UKO62755CN5DTX7CAVA5CNFSM5AEE4Y4KYY3PNVWWK3TUL52HS4DFWFIHK3DMKJSXC5LFON2FEZLWNFSXPKTDN5WW2ZLOORPWSZGOFIZ2F7Y.gif]