RTCSV

A Real Time Clock in System Verilog, that drives 6 seven segment displays. Initially it was meant to help verify a PCB version with basic CMOS counters and logic gate ICs but due to design differences the idea was scraped.

Waveforms

Seven Segment Displays

Clock Counters (20:57:00 to 00:00:00)

Shift Register Debouncers for Manual Input

Manual Input

Improvements

• Turn displays off when unecessary (08:30:57 should be 8:30:57)
• Add ability to decrease digits in manual mode
• Automatically set the actual time via a compatible communications interface through an external module