ipq807x: add DVFS support

This patchset adds support for DVFS on the IPQ8074 family.

Its split into HK and AC CPU DTSI as they have different clocks and
voltages.
Currently, a static voltage map is used instead of the CPR as there is no
driver for it to dynamically adjust each range based on the load.

Signed-off-by: Robert Marko <robimarko@gmail.com>

target/linux/ipq807x/config-5.15

@@ -45,6 +45,8 @@ CONFIG_ARM_GIC_V3_ITS_PCI=y
 # CONFIG_ARM_MHU_V2 is not set
 CONFIG_ARM_PSCI_CPUIDLE=y
 CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
 CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_BINARY_PRINTF=y
 CONFIG_BLK_DEV_LOOP=y
@@ -59,6 +61,19 @@ CONFIG_COMMON_CLK=y
 CONFIG_COMMON_CLK_QCOM=y
 # CONFIG_COMPAT_32BIT_TIME is not set
 CONFIG_COREDUMP=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_IDLE=y
 CONFIG_CPU_IDLE_GOV_MENU=y
 CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
@@ -158,6 +173,7 @@ CONFIG_I2C_QUP=y
 CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_IPQ_APSS_6018 is not set
+CONFIG_IPQ_APSS_8074=y
 # CONFIG_IPQ_APSS_PLL is not set
 # CONFIG_IPQ_GCC_4019 is not set
 # CONFIG_IPQ_GCC_6018 is not set
@@ -307,6 +323,7 @@ CONFIG_PINCTRL_MSM=y
 CONFIG_PM=y
 # CONFIG_PM8916_WATCHDOG is not set
 CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
 CONFIG_POWER_RESET=y
 # CONFIG_POWER_RESET_MSM is not set
 # CONFIG_POWER_RESET_QCOM_PON is not set
@@ -455,6 +472,7 @@ CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_UBIFS_FS=y
 CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UCLAMP_TASK is not set
 CONFIG_UNMAP_KERNEL_AT_EL0=y
 CONFIG_USB=y
 CONFIG_USB_COMMON=y

target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+&CPU0 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&CPU1 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&CPU2 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&CPU3 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpus {
+	cpu_opp_table: cpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-1017600000 {
+			opp-hz = /bits/ 64 <1017600000>;
+			opp-microvolt = <704000>;
+			clock-latency-ns = <200000>;
+		};
+		opp-1382400000 {
+			opp-hz = /bits/ 64 <1382400000>;
+			opp-microvolt = <824000>;
+			clock-latency-ns = <200000>;
+		};
+	};
+};

target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+&CPU0 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&CPU1 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&CPU2 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&CPU3 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpus {
+	cpu_opp_table: cpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-1017600000 {
+			opp-hz = /bits/ 64 <1017600000>;
+			opp-microvolt = <704000>;
+			clock-latency-ns = <200000>;
+		};
+		opp-1382400000 {
+			opp-hz = /bits/ 64 <1382400000>;
+			opp-microvolt = <784000>;
+			clock-latency-ns = <200000>;
+		};
+		opp-1651200000 {
+			opp-hz = /bits/ 64 <1651200000>;
+			opp-microvolt = <832000>;
+			clock-latency-ns = <200000>;
+		};
+		opp-1843200000 {
+			opp-hz = /bits/ 64 <1843200000>;
+			opp-microvolt = <880000>;
+			clock-latency-ns = <200000>;
+		};
+		opp-1920000000 {
+			opp-hz = /bits/ 64 <1920000000>;
+			opp-microvolt = <904000>;
+			clock-latency-ns = <200000>;
+		};
+		opp-2208000000 {
+			opp-hz = /bits/ 64 <2208000000>;
+			opp-microvolt = <984000>;
+			clock-latency-ns = <200000>;
+		};
+	};
+};

target/linux/ipq807x/patches-5.15/0130-clk-qcom-clk-alpha-pll-add-support-for-APSS-PLL.patch

@@ -0,0 +1,54 @@
+From 5a127450125f71247b7384930459b892da227e28 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 28 Dec 2021 20:32:46 +0100
+Subject: [PATCH] clk: qcom: clk-alpha-pll: add support for APSS PLL
+
+APSS PLL type will be used by the IPQ8074 APSS driver for providing the
+CPU core clocks and enabling CPU Frequency scaling.
+
+This is ported from the downstream 5.4 kernel.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
+ drivers/clk/qcom/clk-alpha-pll.h |  1 +
+ 2 files changed, 13 insertions(+)
+
+diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
+index 8f65b9bdafce..d2c3eb4cf4af 100644
+--- a/drivers/clk/qcom/clk-alpha-pll.c
++++ b/drivers/clk/qcom/clk-alpha-pll.c
+@@ -139,6 +139,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
+ 		[PLL_OFF_OPMODE] = 0x28,
+ 		[PLL_OFF_STATUS] = 0x38,
+ 	},
++	[CLK_ALPHA_PLL_TYPE_APSS] = {
++		[PLL_OFF_L_VAL] = 0x08,
++		[PLL_OFF_ALPHA_VAL] = 0x10,
++		[PLL_OFF_ALPHA_VAL_U] = 0xff,
++		[PLL_OFF_USER_CTL] = 0x18,
++		[PLL_OFF_USER_CTL_U] = 0xff,
++		[PLL_OFF_CONFIG_CTL] = 0x20,
++		[PLL_OFF_CONFIG_CTL_U] = 0x24,
++		[PLL_OFF_TEST_CTL] = 0x30,
++		[PLL_OFF_TEST_CTL_U] = 0x34,
++		[PLL_OFF_STATUS] = 0x28,
++	},
+ };
+ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
+
+diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
+index 55e4fa47912f..45e4b93253a9 100644
+--- a/drivers/clk/qcom/clk-alpha-pll.h
++++ b/drivers/clk/qcom/clk-alpha-pll.h
+@@ -17,6 +17,7 @@ enum {
+ 	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
+ 	CLK_ALPHA_PLL_TYPE_AGERA,
+ 	CLK_ALPHA_PLL_TYPE_ZONDA,
++	CLK_ALPHA_PLL_TYPE_APSS,
+ 	CLK_ALPHA_PLL_TYPE_MAX,
+ };
+
+-- 
+2.35.1
+

target/linux/ipq807x/patches-5.15/0131-clk-qcom-Add-DT-bindings-for-IPQ8074-APSS-clock-cont.patch

@@ -0,0 +1,36 @@
+From ab17c6d31f07271b42c6c36c9ad785bdc2871e62 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 28 Dec 2021 20:36:45 +0100
+Subject: [PATCH] clk: qcom: Add DT bindings for IPQ8074 APSS clock controller
+
+Add DT-binding for the IPQ8074 APSS clock controller.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+ create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h
+
+diff --git a/include/dt-bindings/clock/qcom,apss-ipq8074.h b/include/dt-bindings/clock/qcom,apss-ipq8074.h
+new file mode 100644
+index 000000000000..df07766b0146
+--- /dev/null
++++ b/include/dt-bindings/clock/qcom,apss-ipq8074.h
+@@ -0,0 +1,14 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
++ */
++
++#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H
++#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H
++
++#define APSS_PLL_EARLY				0
++#define APSS_PLL				1
++#define APCS_ALIAS0_CLK_SRC			2
++#define APCS_ALIAS0_CORE_CLK			3
++
++#endif
+-- 
+2.35.1
+